Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase

Amr M. S. Tossen; Ahmed Ramadan; Rami Fathy Salem

doi:10.1117/12.2009242

29 March 2013 Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase

Amr M. S. Tossen, Ahmed Ramadan, Rami Fathy Salem

Author Affiliations +

Proceedings Volume 8684, Design for Manufacturability through Design-Process Integration VII; 86840B (2013) https://doi.org/10.1117/12.2009242
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

As semiconductor manufacturing migrates to more advanced technology nodes, the performance improvement anticipated from scaling has failed to match expectations. This failure is due to the emergence of layout-dependent effects (LDEs) not encountered in the design flow prior 65nm process node. We propose a novel methodology that allows the early detection of LDEs during schematic creation. Different from all previous works, this methodology accurately calculates LDEs by interfacing interactively with a simulator tool. Our research indicates that no previous works suggested the use of “on-the-fly” simulation, using Eldo Interactive, to study LDEs. In fact, the use of Calibre tools [2] has been suggested to help the designer check certain basic electrical constraints (like matching) under the existence of LDEs, by specifying the matching condition as a comment added to the original Pyxis schematic netlist. [1] These comments are then transformed into verification rules that are added and checked by Calibre. The proposed flow is tested on a 40nm OTA design, with results not only as accurate as those previously obtained from post-layout analysis, but also equal to or better speed of execution, demonstrating the practicality of using “on-the-fly” simulation to detect and resolve LDEs early in the design flow.

Citation Download Citation

Amr M. S. Tossen, Ahmed Ramadan, and Rami Fathy Salem "Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase", Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840B (29 March 2013); https://doi.org/10.1117/12.2009242

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
6 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Device simulation

Molybdenum

Transistors

Field effect transistors

Manufacturing

Semiconductor manufacturing

Visualization

Show All Keywords

Keywords/Phrases

Search In:

Publication Years