In this paper, a 64 state soft decision Viterbi Decoder (VD) system by using a high speed radix-4 Add Compare Select (ACS) architecture is presented. The proposed VD system can support different data rate (from 53.5 Mbps to 480 Mbps) for Multiband Orthogonal Frequency-division Multiplexing (MB-OFDM) Ultra-Wideband (UWB) system when implemented onto the FPGA board. The proposed VD employs efficient two steps Radix 4 architecture, which is responsible of calculating two steps of 64 state Radix 4 Branch Metrics (BM) within one clock cycle. The branch metrics are calculated using a uniform distance measurement algorithm, which equals to the symbol itself when compared to logic-0 and equal to its one’s complement when compared to logic-1. By employing the modified Modulo Normalization algorithm, it is possible to use only a 10- bit memory block to restore each of the 64 state metrics, with the advantage of avoiding errors caused by overflow during the updating process for state metrics, and simplifying the comparator circuit of the ACS unit. The Two Pointer Even Algorithm, which is considered to be very simple and more hardware-efficient than the register exchange algorithm, is used for tracing back the survivor sequence and output the decoded data stream. 3-bit soft decision input sequences are used for gathering the experimental results. The sampling frequency of the MBOFDM UWB system is 528 MHz, by using the proposed two steps Radix 4 VD architecture we can process 4 input signals in parallel within one clock cycle, therefore only 132 MHz operating frequency is needed for the proposed VD system. This will dramatically reduce the dynamic power consumption for hardware implementation. Final results of the implementation show that the proposed VD architecture can support a maximum working frequency of 152.5 MHz on Xilinx XUPV5-LX110T Evaluation Platform.