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26 September 2013 Performance of buried channel n-type MOSFETs in 0.18-μm CMOS image sensor process
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Abstract
Buried channel (BC) MOSFETs are known to have better noise performance than surface channel (SC) MOSFETs when used as source followers in modern Charge Coupled Devices (CCD). CMOS image sensors find increasing range of applications and compete with CCDs in high performance imaging, however BC transistors are rarely used in CMOS. As a part of the development of charge storage using BC CCDs in CMOS, we designed and manufactured deep depletion BC n-type MOSFETs in 0.18 μm CMOS image sensor process. The transistors are designed in a way similar to the source followers in a typical BC CCD. In this paper we report the results from their characterization and compare with enhancement mode and “zero-threshold” SC devices. In addition to the detailed current-voltage and noise measurements, semiconductor device simulation results are presented to illustrate and understand the different conditions affecting the channel conduction and the noise performance of the BC transistors at low operating voltages. We show that the biasing of the BC transistors has to be carefully adjusted for optimal operation, and that their noise performance at the right operating conditions can be superior to SC devices, despite their lower gain as in-pixel source followers.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Konstantin D. Stefanov, Zhige Zhang, Chris Damerell, David Burt, and Arjun Kar-Roy "Performance of buried channel n-type MOSFETs in 0.18-μm CMOS image sensor process", Proc. SPIE 8859, UV, X-Ray, and Gamma-Ray Space Instrumentation for Astronomy XVIII, 88590I (26 September 2013); https://doi.org/10.1117/12.2024192
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