Design and optimization of four-transistor pixel for low image lag CMOS image sensor

Chao Xu; Jiangtao Xu; Suying Yao; Jing Gao; Zhiyuan Gao

doi:10.1117/12.2030814

11 September 2013 Design and optimization of four-transistor pixel for low image lag CMOS image sensor

Chao Xu, Jiangtao Xu, Suying Yao, Jing Gao, Zhiyuan Gao

Proceedings Volume 8907, International Symposium on Photoelectronic Detection and Imaging 2013: Infrared Imaging and Applications; 89070G (2013) https://doi.org/10.1117/12.2030814
Event: ISPDI 2013 - Fifth International Symposium on Photoelectronic Detection and Imaging, 2013, Beijing, China

Abstract

In four-transistor (4T) CMOS image sensors (CIS), incomplete charge transfer from the photodiode (PD) to the floating diffusion (FD) node can result in image lag, which is a serious problem affecting the imaging performance. In the paper a low image lag 4T pixel structure for CIS is proposed. Two techniques are adopted to promote complete charge transfer in a 4T pixel. Firstly, the threshold voltage of the reset transistor in the 4T pixel is adjusted to an appropriate negative value to realize a high potential in the FD, which is helpful for the charge (electron) to transfer into FD. Inevitably, a large negative threshold voltage make the source-drain leakage current of the reset transistor can not be ignored. In the design the threshold voltage is chosen to satisfy the requirements of a higher potential in FD and a lower source-drain leakage current of reset transistor simultaneously. Secondly, an additional p-type layer is adopted on the surface of the photodiode, with partially overlapped the channel of the transfer transistor. With an optimized overlap length, neither an apparent potential barrier nor a severe potential pocket can be formed on the route of charge transfer. So a potential distribution under transfer gate conducive to charge transfer is achieved. An identical photomask is used to manufacture the additional p-type layer and the p-type pinned layer of the photodiode, and the latter is formed in selfaligned way, which is economic in process and helpful to control the misalignment of the layer. The simulations are completed in Technology Computer-Aided Design (TCAD) tools. A test chip with 32×10 pixel array has been designed and fabricated in 0.18μm 1P4M CIS process. The experimental results demonstrate that the image lag is below the measurement threshold (using 12-bit ADC) with an additional reset operation adopted. Without the additional reset, the largest measured image lag is 0.18%.

Citation Download Citation

Chao Xu, Jiangtao Xu, Suying Yao, Jing Gao, and Zhiyuan Gao "Design and optimization of four-transistor pixel for low image lag CMOS image sensor", Proc. SPIE 8907, International Symposium on Photoelectronic Detection and Imaging 2013: Infrared Imaging and Applications, 89070G (11 September 2013); https://doi.org/10.1117/12.2030814

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