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27 February 2014 VCSEL arrays for high-aggregate bandwidth of up to 1.34 Tbps
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Even though the lane speed of VCSEL based AOC and transceivers has reached 25 Gbps and beyond [1-7], parallel optics are getting even more important in order to meet the increasing demand for aggregate bandwidths in upcoming applications, among others, 100 Gigabit Ethernet, Infiniband EDR, or EOM (embedded optical modules). As 100 Gbps can be achieved by, e.g., 4 times 25 Gbps using standard QSFP form factor, different approaches are using large scale 2D VCSEL arrays operating at lower lane speeds. Early work on 2D VCSEL based transceivers has already been presented beginning of this century [8] and recent work also addressed the potential of this technology [9,10]. In 2013, Compass EOS has introduced a 1.34 Tbps core router solution [11,12,13] that incorporates 2D VCSEL arrays of 14x12 emitters designed and manufactured by Philips U-L-M Photonics. The VCSEL array is mounted face down onto a CMOS ASIC, directly on top of the analog area. The emission wavelength of 1000 nm allows for substrate side emission and thus for flip-chip mounting as well as the possibility of integrating 2D microlens arrays onto the stack of CMOS and VCSEL array. After briefly introducing the router with regard to the incorporated VCSEL technology we discuss the design and performance of the VCSEL array. Finally, the assembly solution for this most compact and dense transceiver solution is presented.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Martin Grabherr, Steffan Intemann, Roger King, Stefan Wabra, Roland Jäger, and Michael Riedl "VCSEL arrays for high-aggregate bandwidth of up to 1.34 Tbps", Proc. SPIE 9001, Vertical-Cavity Surface-Emitting Lasers XVIII, 900105 (27 February 2014);


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