Paper
2 April 2014 Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process
Hsiao-Chiang Lin, Yang-Liang Li, Shiuan-Chuan Wang, Chien-Hung Liu, Zih-Song Wang, Jhung-Yuin Hsuh
Author Affiliations +
Abstract
The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hsiao-Chiang Lin, Yang-Liang Li, Shiuan-Chuan Wang, Chien-Hung Liu, Zih-Song Wang, and Jhung-Yuin Hsuh "Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process", Proc. SPIE 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII, 905026 (2 April 2014); https://doi.org/10.1117/12.2045875
Lens.org Logo
CITATIONS
Cited by 1 scholarly publication.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Semiconducting wafers

Double patterning technology

Scanners

Critical dimension metrology

Lithography

Carbon

Optical lithography

Back to Top