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2 April 2014 CD uniformity optimization at volume ramp up stage for new product introduction
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In this paper we describe the joint development and optimization of the critical dimension uniformity (CDU) at an advanced 300 mm ArFi semiconductor facility of SK Hynix in the high volume device. As the ITRS CDU specification shrinks, semiconductor companies still need to maintain high wafer yield and high performance (hence market value) even during the introduction phase of a new product. This cannot be achieved without continuous improvement of the on-product CDU as one of the main drivers for yield improvement. ASML Imaging Optimizer is one of the most efficient tools to reach this goal. This paper presents experimental results of post-etch CDU improvement by ASML imaging optimizer for immature photolithography and etch processes on critical features of 20nm node. We will show that CDU improvement potential and measured CDU strongly depend on CD fingerprint stability through wafers, lots and time. However, significant CDU optimization can still be achieved, even for variable CD fingerprints. In this paper we will review point-to-point correlation of CD fingerprints as one of the main indicators for CDU improvement potential. We will demonstrate the value of this indicator by comparing CD correlation between wafers used for Imaging Optimizer dose recipe development, predicted and measured CDU for wafers and lots exposed with various delays ranging from a few days to a month. This approach to CDU optimization helps to achieve higher yield earlier in the new product introduction cycle, enables faster technology ramps and thereby improves product time to market.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jin-Soo Kim, Won-Kwang Ma, Young-Sik Kim, Myoung-Soo Kim, Won-Taik Kwon, Sung-Ki Park, Peter Nikolsky, Marian Otter, Maryana Escalante Marun, Roy Anunciado, Kyu-Tae Sun, Greet Storms, and Ewould van West "CD uniformity optimization at volume ramp up stage for new product introduction", Proc. SPIE 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII, 905037 (2 April 2014);


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