Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

Sergio Gómez; Francesc Moll; Juan Mauricio

doi:10.1117/12.2046208

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28 March 2014 Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

Sergio Gómez, Francesc Moll, Juan Mauricio

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Proceedings Volume 9053, Design-Process-Technology Co-optimization for Manufacturability VIII; 90530M (2014) https://doi.org/10.1117/12.2046208
Event: SPIE Advanced Lithography, 2014, San Jose, California, United States

Abstract

A yield estimation model to evaluate the lithography distortion in a printed layout is presented. The yield model relates the probability of non-failure of a lithography hotspot with the manufacturing yield loss. We define a lithography hotspot as a pattern construct with excessive variation under lithography printing using lithography simulations. Thereby, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho-degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the manufacturing yield and increases the number of good dies per wafer.

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Sergio Gómez, Francesc Moll, and Juan Mauricio "Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations", Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530M (28 March 2014); https://doi.org/10.1117/12.2046208

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