This PDF file contains the front matter associated with SPIE Proceedings Volume 9054 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.

Among the different next generation lithography techniques, multibeam may arise as a cost effective solution to pattern sub-22nm technological nodes. A low LWR is required to keep downscaling. In this study, capability of producing low LWR 32/32nm L/S patterns with two different ebeam tools was evaluated. One state-of-the-art single variable shapedbeam (50kV) VISTEC SB3054 and a multiple Gaussian beam MAPPER ASTERIX pre-alpha tool (5kV) are used. Thanks to the great flexibility of e-beam lithography, exposure of biased designs in which the exposed area is reduced is carried out. Such exposure strategy showed a great effectiveness to lower LWR (down to around 3.0nm). To reduce further LWR some post litho-treatments such as thermal processing, plasma treatments and UV treatments are used on patterns exposed with VISTEC SB3054. A combination of a biased exposure and post-litho treatments reduced initial 4.8nm LWR down to 2.8nm (41.7% reduction). Once complete the LWR reduction protocol will be transferred on MAPPER exposures.

One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma. It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc…) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1]. In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate / poly-silicon / oxide hard mask stack. We will show that modifying the resist-cure / Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.

Amorphous silicon (a-Si) gates with a length of 20nm have been obtained in a ‘line & cut’ double patterning process. The first pattern was printed with EUV photoresist and had a critical dimension close to 30nm, which imposed a triple challenge on the etch: limited photoresist budget, high line width roughness and significant CD reduction. Combining a plasma pre-etch treatment of the photoresist with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Planar Fully-Depleted (FD) Silicon On Insulator (SOI) MOSFET technology has already demonstrated large performance boost vs bulk at 28nm node (>30%) and is very competitive for incoming mobile & multimedia products thanks to design porting from bulk. Indeed, FDSOI is very attractive for low power applications due to its low sub threshold slope (~60mV/dec), better short channel effect (SCE) control and reduced junction capacitance. 28nm FDSOI devices highly depend on gate CD morphology because electrical effective gate length is driven by metal gate CD. High-k metal gate etching is therefore a key point to achieve these requirements. Gate profiles and metal gate CD control are mandatory and variability has to be minimized across the wafer (WiW), wafer to wafer and lot to lot. In this paper, we will focus on metal gate CD variability investigation. Once polysilicon gate profiles are frozen, metal gate profiles adjustment is achieved, based on scatterometry metal gate profiles measurements, TEM analysis and electrical results. Thanks to this methodology, a metal gate etching process has been tuned on 300mm industrial platform etcher. This work was performed at ST Crolles 300 facility in collaboration between STMicroelectronics & CEA/LETI.

Dry development process for directed-self assembly lithography (DSAL) hole shrink process has been studied with focus on etch selectivity of poly(methyl methacrylate) (PMMA) to polystyrene (PS) and suppression of etch stop. Highly selective etch of PMMA to PS was achieved using CO gas chemistry. However, it was found that PMMA etching stopped proceeding beyond a certain depth. Scanning Transmission Electron Microscopy (STEM) and X-ray Photoelectron Spectroscopy (XPS) analysis indicated that a deposition layer formed not only on PS but also on PMMA. H₂ addition to CO plasma proved effective in controlling the deposition layer thickness and suppressing etch stop. CO/H₂ plasma process combined with ion energy control was applied to the dry development process for hole shrink. DSAL dry development process for hole shrink process was successfully realized by designing the etch gas chemistry and controlling ion energy.

Roughness of lithographic lines is typically expressed as the absolute 3σ value variation of the resist lines. It was found that this 3σ value gives a good general indication of roughness across the wafer. However, it is important to have a full characterization of the roughness in the frequency domain. This necessity arises from the requirement to reduce different roughness frequencies for various lithographic levels. A power spectral density analysis is used to evaluate the effect of post-lithography plasma treatment processes on roughness evolution of 22 nm lines. It is found that the wafer to wafer roughness distribution after lithographic exposure is very stable for two types of extreme ultraviolet photoresists. Furthermore, by comparing various plasma processes, hydrogen based plasma was found to reduce mid and high frequency roughness contributions. However, the lithographic scaling towards smaller dimensions also causes the constriction of lithographic requirements which induces a limited roughness improvement. Nevertheless, power spectral density (PSD) analysis is found to give additional information.

In this work, we have investigated the evolution of line roughness from e-beam lithography to final gate patterning based on conventional SiO₂/Si₃N₄/SiO₂ (ONO) hard mask using a Capacitively Coupled Plasma (CCP) etcher. A severe roughness was observed on gate patterning line when PR patterns were directly transferred into ONO hard mask even if a high etch selectivity of ONO hard mask to PR was used by CF₄/CH₂F₂/Ar plasma. The formation mechanisms of line roughness were presented by a) effect of decomposed oxygen radical from bulk SiO₂ by ion bombardment, b) rough surface morphology of poly-silicon accelerates etch of both hard mask and PR sidewalls by reflected ion. It is found that a combination of a capping layer and α-Si gate can reduce strong dependence on PR mask and eliminate ion reflection effect from rough surface morphology. Our results show that gate pattern indicates a smooth line without deformation and final gate length of 29nm with Line Width Roughness of 3.5nm is achieved.

For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.

This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer’s Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti’s 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

Pores in ultra-low-k carbon-doped silicon oxide (SiOCH) film have been a serious problem because they produce fragile film strength, with the film incurring damage from integration and diffusion of Cu atoms in thermal annealing. To address this problem, we developed a practical large-radius neutral beam enhanced CVD process to precisely control the film structure so as to eliminate any pores in the film. We used the process with dimethoxy-tetramethyl-disiloxane (DMOTMDS) as a precursor to form a SiOCH film on an 8-inch Si wafer and obtained a non-porous film having an ultra-low k-value of 2.2 with sufficient modulus (>10 GPa). Analyzing the film structure by experimental and theoretical techniques showed that symmetric polymethylsilaxane (PMS) chains were grown and cross-linked to each other in the film. This particular film did not incur any damage from acid or alkali solution or oxygen plasma. Furthermore, the dense film almost completely resisted Cu diffusion into it during thermal annealing.

Gas cluster ion beam (GCIB) etching is a technique, which among other attributes, enables advanced process control of feature height uniformity, increasingly critical to sub 16nm FINFET performance. GCIB can have a high local etch rate in a focused beam, which combined with location specific processing (LSP) algorithms, enables high-precision correction of incoming or downstream thickness uniformity. Applications of this technique include trimming of RF filter devices (in production now for over 10 years), as well as emerging applications in thickness control enabling for FINFET device integration. Here we describe the GCIB etch technology and the LSP method and capabilities.

In this paper, we have introduced various plasma source concepts for large-area plasma processing with a brief review of the experimental and simulation results. A multi-radio-frequency (RF) feed design, multi-electrode concepts are suggested to enhance the plasma uniformity, and, a multi-ICP source is introduced for large-area, ultra-low pressure processes to remove standing-wave and skin effects causing the processing output to be non-uniform. Using multi-feeds to connect separated electrodes in a multi-electrode is one method of uniformity control. A multi-plasma source can also be used to increase the plasma uniformity, which makes it possible to enlarge the processing area. A parallel array of the ICP sources can decrease the total impedance of the system and enable a high electron density to be achieved. We discussed the asymmetric factors including the chamber wall potential profile, stray capacitance, and gas distribution. Finally some issues regarding the control of the plasma parameters through adjustment of the excitation frequency and RF power, operating pressure, gas mixing ratio, and other external parameters to optimize large-area plasma processing are mentioned.

Block co-polymer directed self-assembly (BCP DSA) has become an area of fervent research activity as a potential alternative or adjunct to EUV lithography or self-aligned pitch multiplication strategies. This presentation will evaluate two DSA strategies for patterning line-space arrays at 30nm pitch: graphoepitaxial DSA with surface-parallel cylinder BCPs and chemoepitaxial DSA with surface-normal lamellar BCPs. A comparison of pattern transfer into hard-mask and substrate films will be made by consideration of line and space CDs, line profile of cross-sectional SEM images, and comparison of relative LWR/SWR. The processes will be benchmarked against Micron’s process used in manufacturing its 16nm half-pitch NAND part.

Block CoPolymer (BCP) self-assembly creates periodical patterns with feature sizes eventually below 10 nm. On plain substrates, ordering is only obtained in grains not larger than a few micrometers but self-assembly in trenches of a pattern (using so-called graphoepitaxy technique) can create long-range order between the polymer micro-domains. As a result, such directed self-assembly (DSA) approaches may be used as ultra-high resolution patterning schemes in the microelectronics industry. Due to its ease of processing, a large majority of the lithographic BCP work reported so far concerned polystyreneblock- polymethylmethacrylate (PS-b-PMMA). Researchers show now an increased interest to polystyrene-blockpolydimethylsiloxane (PS-b-PDMS) block copolymers due to its improved resolution. In the present study, typical industry-like photolithography stacks are patterned by combining graphoepitaxy with cylindrical PS-b-PDMS BCP and state of the art plasma etching technologies. The industry like photolithography stack is fabricated on 300 mm diameter silicon wafers, and composed of three layers: Spin-On-Carbon (SOC), Siliconcontaining Anti-Reflective Coating (SiARC) and 193 nm photolithography resist. About 60 nm deep trenches are first patterned by plasma etching in the SiARC/SOC stack using the 193 nm photolithography resist mask. These trenches are then used to confine the BCP and guide the self-assembly of horizontal PDMS cylinders. Wetting conditions allows avoiding the interfacial PDMS wetting layer at the bottom and lateral interfaces after the solvent annealing step. Finally, dedicated pulsed plasma etching conditions were developed in order to reveal the BCP patterns, transfer them into the remaining SOC layer under the trenches and finally into the underlying silicon substrate. 15 nm half-pitch dense line/space features are formed with a height up to 105 nm. In conclusion, long-range order line/space features could be produced by using horizontal cylindrical high Flory- Huggins parameter (χ) BCPs combined with industry-type photolithography stacks.

The use of TiN-Hard masks for Cu metal layer patterning has become a common technique for trench first metal hard mask (TFMH) back end of line (BEOL) integration schemas. Resist rework influences the chemical and physical behavior of the TiN hard mask and therefore the final result of the dual damascene etch process in terms of critical line dimension (CD) and trench taper determining the electrical metal sheet resistance. Within this paper, the effects of three different resist rework strip procedures on subsequent TiN hard mask and dual damascene etching, using O₂, H₂N₂ and H₂O plasma processes, are compared. Furthermore, the interaction of the rework process with the CD tuning capabilities in dual damascene etch are evaluated. Summarizing the data, a stable process flow for wafers with and without resist rework is shown, eliminating litho CD rework offsets, resulting in metal trench processing with tight geometrical and electrical distributions.

Progress in lithographic resolution has made the adoption of extremely thin photoresist films necessary for the fabrication of ‘2× nm’ structures to prevent issues such as resist collapse during development. While there are resists with high etch durability, ultimately etch depth is limited by resist thickness. A possible solution is the use of a multilayer etch stack. For organic hardmasks a carbon-rich material is preferred as carbon possesses a high etch resistance in silicon etch plasma processes. In terms of manufacturability it is beneficial to spin coat the carbon layer instead of using chemical vapor deposition, but the presence of carbon-hydrogen bonds in typical spin on carbon leads to line wiggling during the etch. We have previously introduced a fullerene based ‘spin on carbon’ (SoC) with high etch durability and reported on material characterization. Here we show recent advances in material development and work towards commercialization. The low hydrogen level in the material allows for high resolution etching without wiggling.

In this paper, we demonstrate the unique advantage of dual-frequency mid-gap capacitively coupled plasma (m-CCP) in advanced node patterning process with regard to etch rate / depth uniformity and critical dimension (CD) control in conjunction with wider process window for aspect ratio dependent & microloading effects. Unlike the non-planar plasma sources, the simple design of the mid-gap CCPs enables both metal and non-metal hard-mask based patterning, which provides essential flexibility for conventional and DSA patterning. We present data on both, the conventional multi patterning as well as DSA patterning for trenches / fins and holes. Rigorous CD control and CDU is shown to be crucial for multi patterning as they lead to undesirable odd-even delta and pitch walking. For DSA patterning, co-optimized N_e / V_dc of the dual frequency CCPs would be demonstrated to be advantageous for higher organic-to-organic selectivity during co-polymer etching.