Translator Disclaimer
Paper
10 September 2014 Mk x Nk gated CMOS imager
Author Affiliations +
Abstract
Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James Janesick, Tom Elliott, James Andrews, John Tower, Perry Bell, Alan Teruya, Joe Kimbrough, and Jeanne Bishop "Mk x Nk gated CMOS imager", Proc. SPIE 9211, Target Diagnostics Physics and Engineering for Inertial Confinement Fusion III, 921106 (10 September 2014); https://doi.org/10.1117/12.2063524
PROCEEDINGS
13 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

Incoherent Electro-Optical Processing: A Tutorial
Proceedings of SPIE (December 28 1982)
Ultrahigh-speed CMOS scanning linear imager family
Proceedings of SPIE (May 15 2001)
Design And Development Of A 1024 X 1024 Visible Imager
Proceedings of SPIE (November 08 1984)
4-million-pixel CCD array for scientific applications
Proceedings of SPIE (July 12 1993)
Design of 300 frames per second 16 port CCD video...
Proceedings of SPIE (August 18 2011)

Back to Top