This PDF file contains the front matter associated with SPIE Proceedings Volume 9231, including the Title Page, Copyright information, Table of Contents, Authors, Conference Committee, and Foreword.

Photomask is at the heart of a lithographic scanner’s optical path. It cannot be left non-optimized from the imaging point of view. In this work we provide new insights on two critical aspects of EUV mask architecture: optimization of absorber for 16 nm half-pitch imaging and a systematic approach to black border EUV and DUV reflectance specifications. Good 16 nm imaging is demonstrated on ASML NXE:3300 EUV scanner. Currently a relatively high dose resist is used for imaging and the dose reduction is desired. Optimization (reduction) of absorber height and mask CD bias can allow for up to 30% dose reduction without essential contrast loss. Disadvantages of absorber height reduction are ~7 nm increase of best focus range through pitch and tighter absorber height mean to target and uniformity requirements. A disadvantage of a smaller reticle CD (down to 14 nm 1x) is manufacturing process uniformity over the reticle. A systematic approach of black border reflections impact on imaging is established. The image border is a pattern free dark area surrounding the image field and preventing exposure of the image field neighborhood on wafer. Currently accepted design of the black border on EUV reticle is an image border where the absorber and multilayer stack are etched down to the substrate and EUV reflectance is reduced to <0.05%. DUV reflectance of such a black border is about 5%. It is shown that a tighter DUV reflectance specification <1.5% is required driven by the impact of DUV reflections from the black border on imaging. NXE:3300 and NXE:3100 experimental imaging results are shown. The need of low DUV wavelength reflectance metrology (in the range 100-300 nm) is demonstrated using an estimated NXE scanner out-of-band DUV spectrum. Promising results of low DUV reflectance of the black border are shown.

Extreme Ultraviolet Lithography (EUVL) has been in the making for more than a quarter century. The first EUVL production tools have been delivered over the past year and chip manufacturers and suppliers are maturing the technology in pilot line mode to prepare for high volume manufacturing (HVM). While excellent progress has been made in many technical and business areas to prepare EUVL for HVM introduction, there are still critical technical and business challenges to be addressed before the industry will be able to use EUVL in HVM.

Many experts claim that the 28nm technology node will be the most cost effective technology node forever. This results from primarily from the cost of manufacturing due to the fact that 28nm is the last true Single Patterning (SP) node. It is also affected by the dramatic increase of design costs and the limited shrink factor of the next following nodes. Thus, it is assumed that this technology still will be alive still for many years. To be cost competitive, high yields are mandatory. Meanwhile, leading edge foundries have optimized the yield of the 28nm node to such a level that that it is nearly exclusively defined by random defectivity. However, it was a long way to go to come to that level. In my talk I will concentrate on the contribution of lithography to this yield learning curve. I will choose a critical metal patterning application. I will show what was needed to optimize the process window to a level beyond the usual OPC model work that was common on previous nodes. Reducing the process (in particular focus) variability is a complementary need. It will be shown which improvements were needed in tooling, process control and design-mask-wafer interaction to remove all systematic yield detractors. Over the last couple of years new scanner platforms were introduced that were targeted for both better productivity and better parametric performance. But this was not a clear run-path. It needed some extra affords of the tool suppliers together with the Fab to bring the tool variability down to the necessary level. Another important topic to reduce variability is the interaction of wafer none-planarity and lithography optimization. Having an accurate knowledge of within die topography is essential for optimum patterning. By completing both the variability reduction work and the process window enhancement work we were able to transfer the original marginal process budget to a robust positive budget and thus ensuring high yield and low costs.

Historical data indicates reticle write times are increasing node-to-node. The cost of mask sets is increasing driven by the tighter requirements and more levels. The regular introduction of new generations of mask patterning tools with improved performance is unable to fully compensate for the increased data and complexity required. Write time is a primary metric that drives mask fabrication speed. Design (Raw data) is only the first step in the process and many interactions between mask and wafer technology such as OPC used, OPC efficiency for writers, fracture engines, and actual field size used drive total write time. Yield, technology, and inspection rules drive the remaining raw cycle time. Yield can be even more critical for speed of delivery as it drives re-writes and wasted time. While intrinsic process yield is important, repair capability is the reason mask delivery is still able to deliver 100% good reticles to the fab. Advanced nodes utilizing several layers of multiple patterning may require mask writer tool dedication to meet image placement specifications. This will increase the effective mask cycle time for a layer mask set and drive the need for additional mask write capability in order to deliver masks at the rate required by the wafer fab production schedules.

The scaling of semiconductor devices is slowing down because of the difficulty in establishing their functionality at the nano-size level and also because of the limitations in fabrications, mainly the delay of EUV lithography. While multigate devices (FinFET) are currently the main driver for scalability, other types of devices, such as 3D devices, are being realized to relax the scaling of the node. In lithography, double or multiple patterning using ArF immersion scanners is still a realistic solution offered for the hp16nm node fabrication. Other lithography candidates are those called NGL (Next Generation Lithography), such as DSA (Directed-Self-Assembling) or nanoimprint. In such situations, shot count for mask making by electron beam writers will not increase. Except for some layers, it is not increasing as previously predicted. On the other hand, there is another aspect that increases writing time. The exposure dose for mask writing is getting higher to meet tighter specifications of CD uniformity, in other words, reduce LER. To satisfy these requirements, a new electron beam mask writer, EBM-9000, has been developed for hp16nm/logic11nm generation. Electron optical system, which has the immersion lens system, was evolved from EBM-8000 to achieve higher current density of 800A/cm2. In this paper, recent shot count and dose trend are discussed. Also, writing time is estimated for the requirements in EBM-9000.

The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.

The combination of a reflective photomask with the non-telecentric illumination and arc shaped slit of the EUV scanner introduces what are known as shadowing effects. The compensation of these effects requires proper biasing of the photomask to generate the intended image on the wafer. Thus, the physical pattern on the mask ends up being noticeably different from the desired pattern to be written on the wafer. This difference has a strong dependence on both the illumination settings and the features to be printed. In this work, the impact of shadowing effects from line and space patterns with a nominal CD of 16nm at wafer was investigated with particular focus on the influence of pattern orientation and pitch, illumination pupil shape and fill (coherence) and absorber height. CD, best focus shift and contrast at best focus are utilized in detail in order to study the impact of the shadowing effects. All the simulation cases presented employ a complete scanner arc emulation, i.e. describe the impact of the azimuthal angle component of the illumination arc as in the NXE:3300 scanner and as it can be emulated by the AIMS^TM EUV.

Scanning probe microscopy (SPM) is a promising candidate for accurate assessment of metrology and defects on wafers and masks, however it has traditionally been too slow for high-throughput applications, although recent developments have significantly pushed the speed of SPM [1,2]. In this paper we present new results obtained with our previously presented high-throughput parallel SPM system [3,4] that showcase two key advances that are required for a successful deployment of SPM in high-throughput metrology, defect and mask inspection. The first is a very fast (up to 40 lines/s) image acquisition and a comparison of the image quality as function of speed. Secondly, a fast approach method: measurements of the scan-head approaching the sample from 0.2 and 1.0 mm distance in under 1.4 and 6 seconds respectively.

A new concept of semiconductor lithography is presented. The new technology is tentatively called as New LEEPL since it is an outgrowth of LEEPL which has been developed around 2002. However the new system is completely different from LEEPL. Instead of a single membrane mask used in LEEPL, we use “mask wafer” where mask patterns are made on a wafer by NIL at corresponding positions of chip patterns of chip wafer. The mask patterns on mask wafer have parallel struts structure of 2 division complementary mask (2-DCMPS) Gold (or Si ) dots of thickness of ~50μm are made on the surface of struts and scribing region for equalizing the temperature of mask wafer and chip wafer. Without these contact dots the temperature difference of ~0.5 K will be generated by full power of 1000μA at 2KV. Both mask wafer and chip wafer are cramped together and kept united throughout the processes. The overlay errors between mask patterns and corresponding chip patterns are measured optically. The error map data are fed to 10 e-beam column array to correct the overlay placement errors. Each column does not have main scanning deflector but has tiny deflector only for beam-tilt operation to correct errors. It can deliver 100μA without space charge blur and thus the resolution of L/S pattern of 10nm range can be achieved at resist thickness of 20nm. The e-beam exposure over the mask is performed by the stage motion. Since mask wafer does not have thermal distortion, the thin membrane’s distortion alone will affect the image placement accuracy. In order to obtain less than 1nm distortion of the membrane, the size of 2-DCPS must be smaller 0.7mm.

In this work we report on the strong improvement of pattern quality and significant write-time reduction using Character Projection with a multi-stencil character stage with more than 2000 apertures for the fabrication of nanomaterials and, in particular, on an optical metamaterial, which is called “Metamaterial Perfect Absorber”. The Character Projection ebeam lithography allows the transition from the time-consuming serial to a fast quasi-parallel writing method and opens the way for the fabrication of device areas which are impossible to realize with often in the R&D used SEM based Gaussian electron beam-writers. More than 150.000 times faster than the comparable Gaussian E-beam exposure, 100 times faster and with a factor of 10 improved pattern size homogeneity than the corresponding Variable Shaped E-beam exposure – these are our main results for the fabrication of optical metamaterials using a Variable Shaped E-beam with Character Projection.

Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho – etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

In this article we report the fabrication of large arrays of micro-optical gratings using soft embossing with elastic Polydimethylsiloxane (PDMS) molds and ultra-violet (UV) curable resins. Three different kinds of resins are used to replicate the master gratings in a process akin to a roll to roll process. The optical surface profiling measurements show that the dimensions of the replicated gratings closely approximate those of the master gratings. Optical diffractions of these gratings are also measured and analyzed.

This study quantifies the impact of systematic mask errors on OPC model accuracy and proposes a methodology to reconcile the largest errors via calibration to the mask error signature in wafer data. First, we examine through simulation, the impact of uncertainties in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data while other variable values are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. It is shown that the wafer simulations are highly dependent upon the 1D/2D representation of the mask, in addition to the mask sidewall for 3D mask models. In addition, this paper demonstrates substantial accuracy improvements in the 3D mask model using physical perturbations of the input mask geometry when using Domain Decomposition Method (DDM) techniques. Results from four test cases demonstrate that small, direct modifications in the input mask stack slope and edge location can result in model calibration and verification accuracy benefit of up to 30%. We highlight the benefits of a more accurate description of the 3D EMF near field with crosstalk in model calibration and impact as a function of mask dimensions. The result is a useful technique to align DDM mask model accuracy with physical mask dimensions and scattering via model calibration.

Aerial image can be calculated by either Abbe’s method or sum of coherent system decomposition (SOCS) method for partial coherent system. This paper introduces a programming with Matlab code that changes the analytical representation of Abbe’s method to the matrix form, which has advantages for both Abbe’s method and SOCS since matrix calculation is easier than double integration over object plane or pupil plane. First a singular matrix P is derived from a pupil function and effective light source in the spatial frequency domain. By applying Singular Value Decomposition (SVD) to the matrix P, eigenvalues and eigenfunctions are obtained. The aerial image can then be computed by the eigenvalues and eigenfunctions without calculation of Transmission Cross Coefficient (TCC). The aerial final image is almost identical as an original cross mask and the intensity distribution on image plane shows that it is almost uniform across the linewidth of the mask.

Critical dimension and line edge roughness on photomask arrays are determined with Mueller matrix spectroscopic ellipsometry. Arrays with large sinusoidal perturbations are measured for different azimuth angels and compared with simulations based on rigorous coupled wave analysis. Experiment and simulation show that line edge roughness leads to characteristic changes in the different Mueller matrix elements. The influence of line edge roughness is interpreted as an increase of isotropic character of the sample. The changes in the Mueller matrix elements are very similar when the arrays are statistically perturbed with rms roughness values in the nanometer range suggesting that the results on the sinusoidal test structures are also relevant for “real” mask errors. Critical dimension errors and line edge roughness have similar impact on the SE MM measurement. To distinguish between both deviations, a strategy based on the calculation of sensitivities and correlation coefficients for all Mueller matrix elements is shown. The Mueller matrix elements M₁₃/M₃₁ and M₃₄/M₄₃ are the most suitable elements due to their high sensitivities to critical dimension errors and line edge roughness and, at the same time, to a low correlation coefficient between both influences. From the simulated sensitivities, it is estimated that the measurement accuracy has to be in the order of 0.01 and 0.001 for the detection of 1 nm critical dimension error and 1 nm line edge roughness, respectively.

Non-imaging techniques like X-ray scattering are supposed to play an important role in the further development of CD metrology for the semiconductor industry. GISAXS provides directly assessable information on structure roughness and long-range periodic perturbations. The disadvantage of the method is the large footprint of the X-ray beam on the sample due to the extremely shallow angle of incidence. This can be overcome by using wavelengths in the extreme ultraviolet (EUV) spectral range which allow for much steeper angles of incidence but preserve the large range of momentum transfer that can be observed. At the Physikalisch-Technische Bundesanstalt (PTB), the available photon energy range extends from 50 eV up to 10 keV at two adjacent beamlines. PTB commissioned a new versatile Ellipso-Scatterometer which is capable of measuring 6” square substrates in a clean, hydrocarbon-free environment with full flexibility regarding the direction of the incident light polarization. The reconstruction of line profiles using a geometrical model with six free parameters, a finite element method (FEM) Maxwell solver and least-squares optimization yielded consistent results for EUV and deep ultraviolet (DUV) scatterometry. For EUV photomasks, the actinic wavelength EUV scatterometry yields particular advantages. A significant polarization dependence of the diffraction intensities for 0^th and +1^st orders in the geometry with the grating lines perpendicular to the plane of reflection is observed and the 0^th order intensity shows sufficient sensitivity to the line width such that a CD-resolution below 0.1 nm is within reach. In this contribution we present scatterometry data for line gratings using GISAXS, and EUV and DUV scatterometry and consistent reconstruction results of the line geometry for EUV and DUV scatterometry.

According to the ITRS roadmap [1], the overlay requirement for the 28nm node is 8nm. If we compare this number with the performance given by tool vendors for their most advanced immersion systems (which is < 3nm), there seems to remain a large margin. Does that mean that today’s leading edge Fab has an easy life? Unfortunately not, as other contributors affecting overlay are emerging. Mask contributions and so-called non-linear wafer distortions are known effects that can impact overlay quite significantly. Furthermore, it is often forgotten that downstream (post-litho) processes can impact the overlay as well. Thus, it can be required to compensate for the effects of subsequent processes already at the lithography operation. Within our paper, we will briefly touch on the wafer distortion topic and discuss the limitations of lithography compensation techniques such as higher order corrections versus solving the root cause of the distortions. The primary focus will be on the impact of the etch processes on the pattern placement error. We will show how individual layers can get affected differently by showing typical wafer signatures. However, in contrast to the above-mentioned wafer distortion topic, lithographic compensation techniques can be highly effective to reduce the placement error significantly towards acceptable levels (see Figure 1). Finally we will discuss the overall overlay budget for a 28nm contact to gate case by taking the impact of the individual process contributors into account.

Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVG®NT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 μm across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG®40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

There has been significant research in the area of modeling self-assembling molecular systems. Directed self-assembly (DSA) has proven to be a promising candidate for cost reduction of processes which use double patterning and an enabler of new technology nodes. Self-consistent field theory and Monte Carlo simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-b-PMMA diblock copolymer system needs. The compact model’s main objectives are to find the guiding pattern that produces the lowest possible placement error, as well as verifying that the intended target structures are present after processing. Given that masks are not perfect, and lithographic process variations are not negligible, it is necessary to understand the mask requirements and the types of Optical Proximity Correction techniques that will be used to build guiding patterns. This paper explores the guiding pattern conditions under which proper assembly is achieved, and how the compact model formulation is able to determine placement of reliably assembling structures as well as identification of the guiding patterns which lead to improper assembly. The research leading to these results has been performed in the frame of the industrial collaborative consortium IDeAL focused on the development of Directed Self-assembly technique by block copolymers.

Directed Self Assembly (DSA) of Block Co-Polymers (BCP) has become an intense field of study as a potential patterning solution for future generation devices. The most critical challenges that need to be understood and controlled include pattern placement accuracy, achieving low defectivity in DSA patterns and how to implement this process as a patterning solution. The DSA program at imec includes efforts on these three major topics. Specifically, in this paper the progress for the templated DSA flow within the imec program will be discussed. An experimental assessment is made based on a 37 nm BCP pitch material. In particular, the impact of different process options is illustrated, and data for CD and placement accuracy of the DSA holes in their template is provided.

In our study we have investigated the mask 3D impact on best focus (BF) shifts, which may occur on more complex 2D patterns, by looking at simplified line/space test patterns at various pitches. Several test masks were created; with different absorber thicknesses or different quartz etch depths, all containing ASML L/S test patterns. These test patterns consist of 40 and 45nm horizontal lines at multiple pitches (80-315 nm) and 90nm vertical lines. Wafers were exposed on an NXT:1950i, and the critical dimensions (CDs) were measured through focus to get the best focus (Bossung top) for the different features. In this paper we demonstrate that optimizing the mask absorber thickness for 6% att.PSM will reduce feature-to-feature best focus offsets (~25nm smaller BF range measured on L/S test features) and thus improve the Overlapping Depth of Focus. The change in absorber thickness has limited impact on exposure latitude, but will impact the print CDs. Next to the impact of the absorber thickness on best focus shifts we also derived a 1.33 nm/nm sensitivity of the best focus range to etch depth variations for the ASML L/S test features, and show that the over-etch needs to be carefully controlled, as it also impacts the best focus range.

Directed self assembly has become a very attractive technology for Fin and contact/via applications. Some of the issues related to pattern placement error, defectivity rates and process integration are actively being addressed by the industry and have not faced significant roadblocks for contact-hole applications. While many DSA applications have been proposed, deploying DSA for Fin structures competes in cost and variability control with SADP techniques. Given the 1D nature of find structures, it is difficult to control fin placement with accuracy better than 4nm 3 sigma. In addition, a second patterning step is needed to remove the un-wanted sections of the grating and leaving behind only the required fin structures, therefore limiting its adoption. On the other hand, DSA applied to contact/via holes has demonstrated low defectivity rates due to improved polymerization and processing techniques, as well as an adequate control to reduce the placement error due to thermal fluctuations during the annealing and cylinder formation process. For that reason, the results from contact/via layers can extend to the metal cut layer printing with DSA grapho-epitaxy. In this paper, we show that DSA provides a promising cost-effective solution for the technology scaling by reducing mask number from N to N-1. It is shown that pxOPC may provide better guiding patterns than the conventional one. In addition, the practical grouping rules for DSA should avoid 2D grouping, avoid putting more than 3 features in a group with different pitches, and avoid grouping features with different sizes. Our recommendations to designers for DSA technology are the following: if the design is to be decomposed with 2 or more DSA masks, then the design rules should be set up in this way: first the minimum pitch is better to be on DSA material’s own natural pitch; second, for each DSA mask, singletons and bar-like grouping shapes with DSA’s natural pitch should be used as much as possible.

The usage of phase fluid based stripping agents to remove photoresists from silicon substrates was studied. Photoresists are required for many silicon based technologies such as MEMS patterning, 3D-Integration or frontend and backend of line semiconductor applications [1]. Although the use of resists is very common, their successful integration often depends on the ability to remove the resist after certain processing steps. On the one hand the resist is changing during subsequent process steps that can cause a thermally activated cross-linking which increases the stripping complexity. Resist removal is also challenging after the formation of a hard polymer surface layer during plasma or implant processes which is called skin or crust [2]. On the other hand the choice of stripping chemistry is often limited due to the presence of functional materials such as metals which can be damaged by aggressive stripping chemistries [3].

Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.