Double-patterning optimization in 20nm SRAM design

Qi Lin; Toshiyuki Hisamura; Nui Chong; Hans Pan; Yun Wu; Jonathan Chang; Xin Wu

doi:10.1117/12.2066262

16 September 2014 Double-patterning optimization in 20nm SRAM design

Qi Lin, Toshiyuki Hisamura, Nui Chong, Hans Pan, Yun Wu, Jonathan Chang, Xin Wu

Author Affiliations +

Proceedings Volume 9235, Photomask Technology 2014; 923505 (2014) https://doi.org/10.1117/12.2066262
Event: SPIE Photomask Technology, 2014, Monterey, California, United States

Abstract

As the semiconductor critical dimension (CD) is shrunk to 20nm node and beyond, double and triple patterning technologies become necessary for current 193nm optical lithography. However, the new technologies induce a new variation factor of the two or three mask pattern mismatching in terms of the wafer CD or alignment performance on silicon. This mismatch can degrade matching circuit performance such as SRAM and analog circuit. In this paper, we address the impact on our 20nm CRAM (configuration RAM used in FPGA circuit) performance caused by diffusion layer pattern decomposition (coloring). Furthermore, we propose a methodology to optimize the coloring based on an alignment performance assessment and CD control of two mask patterns printed on silicon wafer. In the same experiment, we observed that the OPC (Optical Proximity Correction) is also critical to the coloring methodology. The silicon results show that after the optimization, the impact of coloring-induced mismatch on CRAM performance can be reduced significantly.

Citation Download Citation

Qi Lin, Toshiyuki Hisamura, Nui Chong, Hans Pan, Yun Wu, Jonathan Chang, and Xin Wu "Double-patterning optimization in 20nm SRAM design", Proc. SPIE 9235, Photomask Technology 2014, 923505 (16 September 2014); https://doi.org/10.1117/12.2066262

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