14-bit pipeline-SAR ADC for image sensor readout circuits

Gengyun Wang; Can Peng; Tianzhao Liu; Cheng Ma; Ning Ding; Yuchun Chang

doi:10.1117/12.2083307

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13 March 2015 14-bit pipeline-SAR ADC for image sensor readout circuits

Gengyun Wang, Can Peng, Tianzhao Liu, Cheng Ma, Ning Ding, Yuchun Chang

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Proceedings Volume 9403, Image Sensors and Imaging Systems 2015; 94030L (2015) https://doi.org/10.1117/12.2083307
Event: SPIE/IS&T Electronic Imaging, 2015, San Francisco, California, United States

Abstract

A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.

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Gengyun Wang, Can Peng, Tianzhao Liu, Cheng Ma, Ning Ding, and Yuchun Chang "14-bit pipeline-SAR ADC for image sensor readout circuits", Proc. SPIE 9403, Image Sensors and Imaging Systems 2015, 94030L (13 March 2015); https://doi.org/10.1117/12.2083307

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