Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

Guido Belfiore; Laszlo Szilagyi; Ronny Henker; Frank Ellinger

doi:10.1117/12.2202800

Translator Disclaimer

11 September 2015 Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

Guido Belfiore, Laszlo Szilagyi, Ronny Henker, Frank Ellinger

Author Affiliations +

Proceedings Volume 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015; 966208 (2015) https://doi.org/10.1117/12.2202800
Event: XXXVI Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (Wilga 2015), 2015, Wilga, Poland

Abstract

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (BER < 10 ^-12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 2⁷ -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Citation Download Citation

Guido Belfiore, Laszlo Szilagyi, Ronny Henker, and Frank Ellinger "Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect", Proc. SPIE 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 966208 (11 September 2015); https://doi.org/10.1117/12.2202800

ACCESS THE FULL ARTICLE