Multi-variants synthesis of Petri nets for FPGA devices

Arkadiusz Bukowiec; Michał Doligalski

doi:10.1117/12.2205612

11 September 2015 Multi-variants synthesis of Petri nets for FPGA devices

Arkadiusz Bukowiec, Michał Doligalski

Proceedings Volume 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015; 96623K (2015) https://doi.org/10.1117/12.2205612
Event: XXXVI Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (Wilga 2015), 2015, Wilga, Poland

Abstract

There is presented new method of synthesis of application specific logic controllers for FPGA devices. The specification of control algorithm is made with use of control interpreted Petri net (PT type). It allows specifying parallel processes in easy way. The Petri net is decomposed into state-machine type subnets. In this case, each subnet represents one parallel process. For this purpose there are applied algorithms of coloring of Petri nets. There are presented two approaches of such decomposition: with doublers of macroplaces or with one global wait place. Next, subnets are implemented into two-level logic circuit of the controller. The levels of logic circuit are obtained as a result of its architectural decomposition. The first level combinational circuit is responsible for generation of next places and second level decoder is responsible for generation output symbols. There are worked out two variants of such circuits: with one shared operational memory or with many flexible distributed memories as a decoder. Variants of Petri net decomposition and structures of logic circuits can be combined together without any restrictions. It leads to existence of four variants of multi-variants synthesis.

Citation Download Citation

Arkadiusz Bukowiec and Michał Doligalski "Multi-variants synthesis of Petri nets for FPGA devices", Proc. SPIE 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 96623K (11 September 2015); https://doi.org/10.1117/12.2205612

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KEYWORDS

Logic

Field programmable gate arrays

Computer programming

High power microwaves

Parallel computing

Clocks

Computer aided design

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