Evaluating system for SRAM-based FPGA single event upset rate

Yunlong Wang; Bin Bao

doi:10.1117/12.2243428

27 September 2016 Evaluating system for SRAM-based FPGA single event upset rate

Yunlong Wang, Bin Bao

Proceedings Volume 9684, 8th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test, Measurement Technology, and Equipment; 968423 (2016) https://doi.org/10.1117/12.2243428
Event: Eighth International Symposium on Advanced Optical Manufacturing and Testing Technology (AOMATT2016), 2016, Suzhou, China

Abstract

This paper takes static random-access-memory (SRAM)-based field-programmable-gate-array (FPGA) as the research object. Attention is focused on the configuration memory of this kind of FPGA, and the research has been devoted to the contents of the configuration memory and the configuration circuit to manage its contents. The single event upset (SEU) happening in the configuration memory doesn’t lead to a functional failure necessarily. The dynamic SEU is SEU which happens in the configuration memory and causes necessarily function failure. This paper introduces a test method of dynamic SUE rate for the SRAM-based FPGA by designing a FPGA with self-test function.

Citation Download Citation

Yunlong Wang and Bin Bao "Evaluating system for SRAM-based FPGA single event upset rate", Proc. SPIE 9684, 8th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test, Measurement Technology, and Equipment, 968423 (27 September 2016); https://doi.org/10.1117/12.2243428

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