Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Sachiko Kobayashi; Motofumi Komori; Inanami Ryoichi; Kyoji Yamashita; Akiko Mimotogi; Ji-Young Im; Masayuki Hatano; Takuya Kono; Shimon Maeda

doi:10.1117/12.2219052

22 March 2016 Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Sachiko Kobayashi, Motofumi Komori, Inanami Ryoichi, Kyoji Yamashita, Akiko Mimotogi, Ji-Young Im, Masayuki Hatano, Takuya Kono, Shimon Maeda

Author Affiliations +

Proceedings Volume 9777, Alternative Lithographic Technologies VIII; 977708 (2016) https://doi.org/10.1117/12.2219052
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

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Sachiko Kobayashi, Motofumi Komori, Inanami Ryoichi, Kyoji Yamashita, Akiko Mimotogi, Ji-Young Im, Masayuki Hatano, Takuya Kono, and Shimon Maeda "Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation", Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 977708 (22 March 2016); https://doi.org/10.1117/12.2219052

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