This PDF file contains the front matter associated with SPIE Proceedings Volume 9778, including the Title Page, Copyright information, Table of Contents, Introduction, and the Conference Committee listing.

There has been 43 years of overlay metrology in microlithography, and how did we get here? This presentation covered three areas: stepper metrology improvements, improved correction potential, and extended feedback loop outside stepper. The presenter went on to discuss where we are today In terms of holistic lithography, as well as where we are going with the future of holistic lithography.

A rigorous electromagnetic simulation method for grating diffraction is presented that concurrently enables appropriate roughness and irregularity modeling. The approach will it make possible for example to overlay surface roughness and or line edge roughness (LER) to regular patterns. In this way, a unique tool is provided to model diffraction and scattering at the same time. It is based on a combination of modal methods such as the RCWA or C-method with near field stitching and subsequent near-to-far field propagation. This paves the way to an efficient and accurate modeling of large scattering areas. Fields of applications are the design of spectrographic gratings as well as optical scatterometry or kindred optical metrology techniques. Examples are provided both for 2D line/space patterns with sinusoidal and blaze profiles and 3D line/space patterns possessing LER and line width roughness (LWR). First ideas are derived how to determine LER and LWR from scatterometric measurements.

Using rigorous coupled wave analysis (RCWA) and finite element method (FEM) simulations together, many interesting ellipsometric measurements can be investigated. This work specifically focuses on simulating copper grating structures that are plasmonically active. Looking at near-field images and Mueller matrix spectra, understanding of physical phenomena is possible. A general strategy for combatting convergence difficulties in RCWA simulations is proposed and applied. The example used is a copper cross-grating structure with known slow convergence.

In recent technology nodes, advanced process and novel integration scheme have challenged the precision limits of conventional metrology; with critical dimensions (CD) of device reduce to sub-nanometer region. Optical metrology has proved its capability to precisely detect intricate details on the complex structures, however, conventional RCWA-based (rigorous coupled wave analysis) scatterometry has the limitations of long time-to-results and lack of flexibility to adapt to wide process variations. Signal Response Metrology (SRM) is a new metrology technique targeted to alleviate the consumption of engineering and computation resources by eliminating geometric/dispersion modeling and spectral simulation from the workflow. This is achieved by directly correlating the spectra acquired from a set of wafers with known process variations encoded. In SPIE 2015, we presented the results of SRM application in lithography metrology and control [1], accomplished the mission of setting up a new measurement recipe of focus/dose monitoring in hours. This work will demonstrate our recent field exploration of SRM implementation in 20nm technology and beyond, including focus metrology for scanner control; post etch geometric profile measurement, and actual device profile metrology.

In this work, capabilities of scatterometry at various steps of the self-aligned quadruple patterning (SAQP) process flow for 7nm (N7) technology node are demonstrated including the pitch walk measurement on the final fin etch step. The scatterometry solutions for each step are verified using reference metrology and the capability to follow the planned process design-of-experiment (DOE) and the sensitivity to catch the small process variations are demonstrated. Pitch walk, which is pitch variation in the four line/space (L/S) populations, is one of the main process challenges for SAQP. Scatterometry, which is a versatile optical technique for critical dimensions (CD) and shape metrology, can find the direct measurement of pitch walk challenging because it is a very weak parameter. In this work, the pitch walk measurement is managed via scatterometry using an advanced technique of parallel interpretation of scatterometry pads with varying pitches. The three populations of trenches could be clearly distinguished with the scatterometry and the consistency with the reference data and with the process DOE are presented. In addition, the root cause of the within-wafer non-uniformity of fin CD is determined. The measurements were done on-site at IMEC as a part of the process development and control of the IMEC SAQP processes [1]. All in all, in this work it is demonstrated that scatterometry is capable of monitoring each process step of FEOL SAQP and it can measure three different space populations separately and extract pitch walk information at the final fin etch step.

We demonstrate hyperspectral coherent imaging in the EUV spectral region for the first time, without the need for hardware-based wavelength separation. This new scheme of spectromicroscopy is the most efficient use of EUV photons for imaging because there is no energy loss from mirrors or monochromatizing optics. An EUV spectral comb from a tabletop high-harmonic source, centered at a wavelength of 30nm, illuminates the sample and the scattered light is collected on a pixel-array detector. Using a lensless imaging technique known as ptychographical information multiplexing, we simultaneously retrieve images of the spectral response of the sample at each individual harmonic. We show that the retrieved spectral amplitude and phase agrees with theoretical predictions. This work demonstrates the power of coherent EUV beams for rapid material identification with nanometer-scale resolution.

The combination of scanning electron microscopy for high spatial resolution, images from multiple angles to provide 3D information, and commercially available stereo photogrammetry software for 3D reconstruction offers promise for nanometer-scale dimensional metrology in 3D. A method is described to test 3D photogrammetry software by the use of virtual samples—mathematical samples from which simulated images are made for use as inputs to the software under test. The virtual sample is constructed by wrapping a rough skin with any desired power spectral density around a smooth near-trapezoidal line with rounded top corners. Reconstruction is performed with images simulated from different angular viewpoints. The software’s reconstructed 3D model is then compared to the known geometry of the virtual sample. Three commercial photogrammetry software packages were tested. Two of them produced results for line height and width that were within close to 1 nm of the correct values. All of the packages exhibited some difficulty in reconstructing details of the surface roughness.

Critical dimension scanning electron microscope (CD-SEM) metrology has long used empirical approaches to determine edge locations. While such solutions are very flexible, physics-based models offer the potential for improved accuracy and precision for specific applications. Here, Monte Carlo simulation is used to generate theoretical linescans from single step and line/space targets in order to build a physics-based analytical model, including the presence of bottom footing and top corner rounding. The resulting analytical linescan model fits the Monte Carlo simulation results for different feature heights, widths, pitches, sidewall angles, bottom footing, and top corner rounding. This model has also been successfully applied to asymetric features such as sidewall spacers encountered in self-aligned double patterning.

Computer simulation of lithographic performance, including resist CD, film thickness, sidewall angle and profile has been extensively studied during the past three decades. Lithography simulation has been widely adopted as an enabling technology for high-volume chip manufacturing. However, measurement artifacts arising from CD-SEM metrology are typically ignored in simulation, due to the difficulty of accurately modeling the effect of the CD-SEM at acceptable computational speed. In this paper, we demonstrate how CD measurements can be improved by including a fast, compact CD-SEM model. For example, the variation in effective resist metrology height along contour lines extracted from a simulated CD-SEM image is characterized for a range of structures through focus. We also demonstrate how SEM settings affect the shape of extracted SEM contour and metrology height at contour edge. The Edge Placement Error (EPE) caused by SEM artifact is carefully studied.

The electric field distribution and charging effects in Scanning Electron Microscopy (SEM) were studied by extending a Monte-Carlo based SEM simulator by a fast and accurate multigrid (MG) based 3D electric field solver. The main focus is on enabling short simulation times with maintaining sufficient accuracy, so that SEM simulation can be used in practical applications. The implementation demonstrates a gain in computation speed, when compared to a Gauss-Seidel based reference solver is roughly factor of 40, with negligible differences in the result (~10⁻⁶ 𝑉). In addition, the simulations were compared with experimental SEM measurements using also complex 3D sample, showing that i) the modelling of e-fields improves the simulation accuracy, and ii) multigrid method provide a significant benefit in terms of simulation time.

In this work we address the computation times of numerical studies in dimensional metrology. In particular, full Monte-Carlo simulation programs for scanning electron microscopy (SEM) image acquisition are known to be notoriously slow. Our quest in reducing the computation time of SEM image simulation has led us to investigate the use of graphics processing units (GPUs) for metrology. We have succeeded in creating a full Monte-Carlo simulation program for SEM images, which runs entirely on a GPU. The physical scattering models of this GPU simulator are identical to a previous CPU-based simulator, which includes the dielectric function model for inelastic scattering and also refinements for low-voltage SEM applications. As a case study for the performance, we considered the simulated exposure of a complex feature: an isolated silicon line with rough sidewalls located on a at silicon substrate. The surface of the rough feature is decomposed into 408 012 triangles. We have used an exposure dose of 6 mC/cm², which corresponds to 6 553 600 primary electrons on average (Poisson distributed). We repeat the simulation for various primary electron energies, 300 eV, 500 eV, 800 eV, 1 keV, 3 keV and 5 keV. At first we run the simulation on a GeForce GTX480 from NVIDIA. The very same simulation is duplicated on our CPU-based program, for which we have used an Intel Xeon X5650. Apart from statistics in the simulation, no difference is found between the CPU and GPU simulated results. The GTX480 generates the images (depending on the primary electron energy) 350 to 425 times faster than a single threaded Intel X5650 CPU. Although this is a tremendous speedup, we actually have not reached the maximum throughput because of the limited amount of available memory on the GTX480. Nevertheless, the speedup enables the fast acquisition of simulated SEM images for metrology. We now have the potential to investigate case studies in CD-SEM metrology, which otherwise would take unreasonable amounts of computation time.

This paper will provide a high level overview of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D) and films metrology, and present the extensive list of applications for which metrology solutions are needed. Commonalities and differences among the various applications will be shown. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment.

We present an extension to ptychography that allows simultaneous deconvolution of multiple, spatially separate, illuminating probes. This enables an increased field of view and hence, an increase in imaging throughput, without increased exposure times. This technique can be used for any non-interfering probes: demonstrated with multiple wavelengths and orthogonal polarizations. The latter of which gives us spatially resolved polarization spectroscopy from a single scan.

We propose a measurement technique which enables the precise determination of side wall angles (SWAs) with absolute values below 1°. Our simulations show that a differentiation between asymmetric SWAs is also possible. The grating structure under investigation has a grating period on the order of a few micrometers. Each grating line consists of a fine sub-grating with 40 nm period and 20 nm critical dimension. Our approach is based on coherent high-NA Fourier scatterometry, extended by a lateral scan over the sample. Additionally, a 180°-shearing element allows for coherent superposition of the higher diffraction orders.

Optical near-field technologies such as solid immersion lenses and hyperlenses are candidate solutions for high resolution and high throughput wafer inspection and metrology for the next technology nodes. Besides sub-diffraction limited optical performance, these concepts share the necessity of extreme proximity to the sample at distances that are measured in tens of nanometers. For the instrument this poses two major challenges: 1) how to measure the distance to the sample? and 2) how to position accurately and at high speed? For the first challenge near-field thermal radiation is proposed as a mechanism for an integrated distance sensor (patent pending). This sensor is realized by making a sensitive calorimeter (accuracy of 2:31nW root sum squared). When used for distance measurement an equivalent uncertainty of 1nm can be achieved for distances smaller than 100 nm. By scanning the distance sensor over the sample, thermal profilometry is realized, which can be used to inspect surfaces in a non-intrusive and non-contact way. This reduces wear of the probe and minimizes the likelihood of damaging the sample.

Coherent extreme ultraviolet beams from tabletop high harmonic generation offer revolutionary capabilities for observing nanoscale systems on their intrinsic length and time scales. By launching and monitoring acoustic waves in such systems, we fully characterize sub-10nm films and find that the Poisson’s ratio of low-k dielectric materials does not stay constant as often assumed, but increases when bond coordination is bellow a critical value. Within the same measurement, by following the heat dissipation dynamics from nano-gratings of width 20-1000nm and different periodicities, we confirm the effects of the newly identified collectively-diffusive regime, where close-spaced nanowires cool faster than widely-spaced ones.

We use EUV coherent microscopy to obtain high-resolution images of buried interfaces, with chemical specificity, in 2+1 dimensions. We perform reflection mode, ptychographic, coherent diffractive imaging with tabletop EUV light, at 29nm, produced by high harmonic generation. Our damascene-style samples consist of copper structures inlaid in SiO₂, polished nearly flat with chemical mechanical polishing. We obtain images of both an unaltered damascene as well as one buried below a 100nm thick layer of evaporated aluminum. The aluminum is opaque to visible light and thick enough that neither optical microscopy, SEM, nor AFM can access the buried interface. EUV microscopy is able to image the buried structures, non-destructively, in conditions where other techniques cannot.

Critical dimension small-angle x-ray scattering (CD-SAXS) with a grazing-incidence geometry, which was recently developed by the authors, has been successfully applied to the cross-sectional profile measurements of different types of L/S- and hole-type patterns on photoresist surfaces. We have calculated diffraction intensities from the nanostructures based on a distorted wave Born approximation method to take the refraction and the reflection at the interfaces between layers into account, and the average cross-sectional profiles have been analyzed by a model-based least-square method. From the precise analyses, slight cross-sectional profile differences of a few nanometers scale generated by using different material and exposure conditions have been identified. The obtained cross-sectional profiles showed good agreements with the results obtained by cross-sectional scanning electron microscopy (SEM). These results demonstrate the applicability of the CD-SAXS to the nanoscale structural metrology. It is expected that the CD-SAXS is also applicable to even smaller scale structures, e.g., those of EUV, NIL, or DSA, as the x-ray wavelength is well shorter than the critical lengths of these structures.

Complexity of process steps integration and material systems for next-generation technology nodes is reaching unprecedented levels, the appetite for higher sampling rates is on the rise, while the process window continues to shrink. Current thickness metrology specifications reach as low as 0.1A for total error budget – breathing new life into an old paradigm with lower visibility for past few metrology nodes: accuracy. Furthermore, for advance nodes there is growing demand to measure film thickness and composition on devices/product instead of surrogate planar simpler pads. Here we extend our earlier work in Hybrid Metrology to the combination of X-Ray based reference technologies (high performance) with optical high volume manufacturing (HVM) workhorse metrology (high throughput). Our stated goal is: put more “eyes” on the wafer (higher sampling) and enable move to films on pattern structure (control what matters). Examples of 1X front-end applications are used to setup and validate the benefits.

Planar fully-depleted silicon-on-insulator (FDSOI) technology potentially offers comparable transistor performance as FinFETs. pFET FDOSI devices are based on a silicon germanium (cSiGe) layer on top of a buried oxide (BOX). Ndoped interfacial layer (IL), high-k (HfO2) layer and the metal gate stacks are then successively built on top of the SiGe layer. In-line metrology is critical in precisely monitoring the thickness and composition of the gate stack and associated underlying layers in order to achieve desired process control. However, any single in-line metrology technique is insufficient to obtain the thickness of IL, high-k, cSiGe layers in addition to Ge% and N-dose in one single measurement. A hybrid approach is therefore needed that combines the capabilities of more than one measurement technique to extract multiple parameters in a given film stack. This paper will discuss the approaches, challenges, and results associated with the first-in-industry implementation of XPS-XRF hybrid metrology for simultaneous detection of high-k thickness, IL thickness, N-dose, cSiGe thickness and %Ge, all in one signal measurement on a FDSOI substrate in a manufacturing fab. Strong correlation to electrical data for one or more of these measured parameters will also be presented, establishing the reliability of this technique.

With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.

By 2017, the critical dimension in patterned wafers will shrink down to 7 nm, which brings great challenges to optics-based defect inspection techniques, due to the ever-decreasing signal to noise ratio with respect to defect size. To continue pushing forward the optics-based metrology technique, it is of great importance to analyze the full characteristics of the scattering field of a wafer with a defect and then to find the most sensitive signal type. In this article, the vector boundary element method is firstly introduced to calculate the scattering field of a patterned wafer at a specific objective plane, after which a vector imaging theory is introduced to calculate the field at an image plane for an imaging system with a high numerical aperture objective lens. The above methods enable the effective modeling of the image for an arbitrary vectorial scattering electromagnetic field coming from the defect pattern of the wafer.

For sub-2Xnm technology nodes, metallic buried voids in metal contacts have become critical yield and reliability issue for high volume semiconductor device manufacturing. Especially as the scaling continues, void-free metal filling becomes more challenging for advanced technology development, which poses great need for effective in-line detection methodology. In this paper we demonstrate comprehensive study of a special buried metallic void detection mode by backscatter electron (BSE) signals based on effective density contrast (EDC), especially for the case of partial conduction while the conventional voltage contrast (VC) mode has no detection due to minimum detectable resistance difference requirement. Successful application of EDC mode in buried metallic void detection by in-line electron beam inspection (EBI) is presented on various metal contact chemical mechanical planarization (CMP) layers, together with Monte Carlo simulations and other characterization methodology which show consistent correlation with experimental observations. Thus an extrapolation based on simulation result is illustrated to predict the detection capability of EDC mode in buried metallic void detection for the popular metal contact material systems including tungsten and copper. Despite of the detection limitation as well as potential damage by the charged particle exposure, EDC mode is demonstrated as a very effective detection methodology for buried metallic void in advanced technology development.

Innovations in nanotechnology are empowering scientists to deepen their understanding of physical, chemical and biological mechanisms. Powerful and precise characterization systems are essential to meet researchers’ requirements. SEEC (Surface Enhanced Ellipsometric Contrast) microscopy is an innovative advanced optical technique based on ellipsometric and interference fringes of Fizeau principles. This technique offers live and label-free topographic imaging of organic, inorganic and biological samples with high Z resolution (down to 0.1nm thickness), and enhanced X-Y detection limit (down to 1.5nm width). This technique has been successfully applied to the study of nanometric films and structures, biological layers, and nano-objects. We applied SEEC technology to different applications explored below.

With decreasing CDOF (Critical Depth Of Focus) for 20/14nm technology and beyond, focus errors are becoming increasingly critical for on-product performance. Current on product focus control techniques in high volume manufacturing are limited; It is difficult to define measurable focus error and optimize focus response on product with existing methods due to lack of credible focus measurement methodologies. Next to developments in imaging and focus control capability of scanners and general tool stability maintenance, on-product focus control improvements are also required to meet on-product imaging specifications. In this paper, we discuss focus monitoring, wafer (edge) fingerprint correction and on-product focus budget analysis through diffraction based focus (DBF) measurement methodology. Several examples will be presented showing better focus response and control on product wafers. Also, a method will be discussed for a focus interlock automation system on product for a high volume manufacturing (HVM) environment.

To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

Line edge roughness (LER) and line width roughness (LWR) are analyzed during pattern transfer in a self-aligned quadruple patterning (SAQP) process. This patterning process leads to a final pitch of 22.5nm, relevant for N7/N5 technologies. Measurements performed by CD SEM (Critical Dimension Scanning Electron Microscope) using different settings in terms of averaging, field of view, and pixel size are compared with reference metrology performed by planar TEM and three-Dimensional Atomic Force Microscope (3D AFM) for each patterning process step in order to investigate the optimal condition for an in-line LWR characterization. Pattern wiggling is als0 quantitatively analyzed during LER/LWR transfer in the SAQP process.

Process-window (PW) evaluation is critical to assess the lithography process quality and limitations. Usual CD-based PW gives only a partial answer. Simulations such as Tachyon LMC (Lithography Manufacturability Check) can efficiently overcome this limitation by analyzing the entire predicted resist contours. But so far experimental measurements did not allow such flexibility. This paper shows an innovative experimental flow, which allows the user to directly validate LMC results across PW for a select group of reference patterns, thereby overcoming the limitations found in the traditional CD-based PW analysis. To evaluate the process window on wafer more accurately, we take advantage of design based metrology and extract experimental contours from the CD-SEM measurements. Then we implement an area metric to quantify the area coverage of the experimental contours with respect to the intended ones, using a defined “sectorization” for the logic structures. This ‘sectorization’ aims to differentiate specific areas on the logic structures being analyzed, such as corners, line-ends, short and long lines. This way, a complete evaluation of the information contained in each CD-SEM picture is performed, without having to discard any information. This solution doesn’t look at the area coverage of an entire feature, but uses a ‘sectorization’ to differentiate specific feature areas such as corners, line-ends, short and long lines, and thus look at those area coverages. An assessment of resist model/OPC quality/process quality at sub nm-level accuracy is rendered possible.

The merits of a robust Statistical Process Control (SPC) methodology have long been established. In response to the numerous SPC rule combinations, processes, and the high cost of containment, the Instability Index (ISTAB) is presented as a tool for managing these complexities. ISTAB focuses limited resources on key issues and provides a window into the stability of manufacturing operations.

ISTAB takes advantage of the statistical nature of processes by comparing the observed average run length (OARL) to the expected run length (ARL), resulting in a gap value called the ISTAB index. The ISTAB index has three characteristic behaviors that are indicative of defects in an SPC instance.

Case 1: The observed average run length is excessively long relative to expectation. ISTAB > 0 is indicating the possibility that the limits are too wide.

Case 2: The observed average run length is consistent with expectation. ISTAB near zero is indicating that the process is stable.

Case 3: The observed average run length is inordinately short relative to expectation. ISTAB < 0 is indicating that the limits are too tight, the process is unstable or both.

The probability distribution of run length is the basis for establishing an ARL. We demonstrate that the geometric distribution is a good approximation to run length across a wide variety of rule sets. Excessively long run lengths are associated with one kind of defect in an SPC instance; inordinately short run lengths are associated with another. A sampling distribution is introduced as a way to quantify excessively long and inordinately short observed run lengths. This paper provides detailed guidance for action limits on these run lengths. ISTAB as a statistical method of review facilitates automated instability detection.

This paper proposes a management system based on ISTAB as an enhancement to more traditional SPC approaches.

Dimensional scaling trends will eventually bring semiconductor critical dimensions (CDs) down to only a few atoms in width. New optical techniques are required to address the measurement and variability for these CDs using sufficiently small in-die metrology targets. Recently, Qin et al. [Light Sci Appl, 5, e16038 (2016)] demonstrated quantitative modelbased measurements of finite sets of lines with features as small as 16 nm using 450 nm wavelength light. This paper uses simulation studies, augmented with experiments at 193 nm wavelength, to adapt and optimize the finite sets of features that work as in-die-capable metrology targets with minimal increases in parametric uncertainty. A finite element based solver for time-harmonic Maxwell’s equations yields two- and three-dimensional simulations of the electromagnetic scattering for optimizing the design of such targets as functions of reduced line lengths, fewer number of lines, fewer focal positions, smaller critical dimensions, and shorter illumination wavelength. Metrology targets that exceeded performance requirements are as short as 3 μm for 193 nm light, feature as few as eight lines, and are extensible to sub-10 nm CDs. Target areas measured at 193 nm can be fifteen times smaller in area than current state-of-the-art scatterometry targets described in the literature. This new methodology is demonstrated to be a promising alternative for optical model-based in-die CD metrology.

Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets requirements, especially at 10nm node due to the 3-d geometry of devices and tight process budget. It has become necessary to measure and control each layer in the gate stack before and after dielectric and metal gate deposition sequences. A typical gate stack can have 5-7 layers including the interfacial layer, high-k dielectric, metal gate stack, work function layers, and cap layers. Similarly, PMOS channel strain is controlled using a graded Si_xGe1-_x stack grown epitaxially over fins in the source/drain regions. This graded stack can have 2-4 layers of different thicknesses and Ge concentrations. This paper discusses the benefit of using spectroscopic ellipsometry with multiple angles of incidence to accurately and precisely determine the thickness of individual layers in critical gate layer stacks at various process steps on planar and grating surfaces. We will also show the benefit of using an advanced laser-based ellipsometer, for ultra-precise measurement of the gate interfacial layer oxides.

Gate-all-around (GAA) nanowire (NW) devices have long been acknowledged as the ultimate device from an electrostatic scaling point of view. The GAA architecture offers improved short channel effect (SCE) immunity compared to single and double gate planar, FinFET, and trigate structures. One attractive proposal for making GAA devices involves the use of a multilayer fin-like structure consisting of layers of Si and SiGe. However, such structures pose various metrology challenges, both geometrical and material. Optical Scatterometry, also called optical critical dimension (OCD) is a fast, accurate and non-destructive in-line metrology technique well suited for GAA integration challenges. In this work, OCD is used as an enabler for the process development of nanowire devices, extending its abilities to learn new material and process aspects specific to this novel device integration. The specific metrology challenges from multiple key steps in the process flow are detailed, along with the corresponding OCD solutions and results. In addition, Low Energy X-Ray Fluorescence (LE-XRF) is applied to process steps before and after the removal of the SiGe layers in order to quantify the amount of Ge present at each step. These results are correlated to OCD measurements of the Ge content, demonstrating that both OCD and LE-XRF are sensitive to Ge content for these applications.

Through-focus scanning optical microscopy (TSOM) shows promise for patterned defect analysis, but it is important to minimize total system noise. TSOM is a three-dimensional shape metrology method that can achieve sub-nanometer measurement sensitivity by analyzing sets of images acquired through-focus using a conventional optical microscope. Here we present a systematic noise-analysis study for optimizing data collection and data processing parameters for TSOM and then demonstrate how the optimized parameters affect defect analysis. We show that the best balance between signalto- noise performance and acquisition time can be achieved by judicious spatial averaging. Correct background-signal subtraction of the imaging-system inhomogeneities is also critical, as well as careful alignment of the constituent images used in differential TSOM analysis.

Optical metrology techniques such as ellipsometry and reflectometry are very powerful for routine process monitoring and control in the modern semiconductor manufacturing industry. However, both methods rely on optical modeling therefore, the optical properties of all materials in the stack need to be characterized a priori or determined during characterization. Some processes such as ion implantation and subsequent annealing produce slight variations in material properties within wafer, wafer-to-wafer, and lot-to-lot; such variation can degrade the dimensional measurement accuracy for both unpatterned optical measurements as well as patterned (2D and 3D) scatterometry measurements. These variations can be accounted for if the optical model of the structure under investigation allows one to extract not just dimensional but also material information already residing within the optical spectra. This paper focuses on modeling of ion implanted and annealed poly Si stacks typically used in high-k technology. Monitoring of ion implantation is often a blind spot in mass production due to capability issues and other limitations of common methods. Typically, the ion implantation dose can be controlled by research-grade ellipsometers with extended infrared range. We demonstrate that multi-channel spectroscopic reflectometry can also be used for ion implant monitoring in the mass-production environment. Our findings are applicable across all technology nodes.

Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed design into a quarter of its original pitch. Due to the number of multiple process steps required for the pitch splitting in SAQP, the process error propagates through each deposition and etch, and accumulates at the final step into structure variations, such as pitch walk and poor critical dimension uniformity (CDU). They can further affect the downstream processes and lower the yield. The impact of this error propagation becomes significant for advanced technology nodes when the process specifications of device design CD requirements are at nanometer scale. Therefore, semiconductor manufacturing demands strict in-line process control to ensure a high process yield and improved performance, which must rely on precise measurements to enable corrective actions and quick decision making for process development. This work aims to provide a comprehensive metrology solution for SAQP.

During SAQP process development, the challenges in conventional in-line metrology techniques start to surface. For instance, critical-dimension scanning electron microscopy (CDSEM) is commonly the first choice for CD and pitch variation control. However, it is found that the high aspect ratio at mandrel level processes and the trench variations after etch prevent the tool from extracting the true bottom edges of the structure in order to report the position shift. On the other hand, while the complex shape and variations can be captured with scatterometry, or optical CD (OCD), the asymmetric features, such as pitch walk, show low sensitivity with strong correlations in scatterometry. X-ray diffraction (XRD) is known to provide useful direct measurements of the pitch walk in crystalline arrays, yet the data analysis is influenced by the incoming geometry and must be used carefully.

A successful implementation of SAQP process control for yield improvement requires the metrology issues to be addressed. By optimizing the measurement parameters and beam configurations, CDSEM measurements distinguish each of the spaces corresponding to the upstream mandrel processes and report their CDs separately to feed back to the process team for the next development cycle. We also utilize the unique capability in scatterometry to measure the structure details in-line and implement a “predictive” process control, which shows a good correlation between the “predictive” measurement and the cross-sections from our design of experiments (DOE). The ability to measure the pitch walk in scatterometry was also demonstrated. This work also explored the frontier of in-line XRD capability by enabling an automatic RSM fitting on tool to output pitch walk values. With these advances in metrology development, we are able to demonstrate the impacts of in-line monitoring in the SAQP process, to shorten the patterning development learning cycle to improve the yield.

For yield improvement of 3D-device manufacturing, metrology for the variability of individual device-features is on hot issue. Transmission Electron Microscope (TEM) can be used for monitoring the individual cross-section. However, efficiency of process monitoring is limited by the speed of measurement including preparation of lamella sample. In this work we demonstrate speedy 3D-profile measurement of individual line-features without the lamella sampling. For instance, we make a-few-micrometer-wide and 45-degree-descending slope in dense line-features by using Focused Ion Beam (FIB) tool capable of 300mm-wafer. On the descending slope, obliquely cut cross-section of the line features appears. Then, we transfer the wafer to Critical-Dimension Secondary Electron Microscope (CDSEM) to measure the oblique cross-section in normal top-down view. As the descending angle is 45 degrees, the oblique cross-section looks like a cross-section normal to the wafer surface. For every single line-features the 3D dimensions are measured. To the reference metrology of the Scanning TEM (STEM), nanometric linearity and precision are confirmed for the height and the width under the hard mask of the line features. Without cleaving wafer the 60 cells on the wafer can be measured in 3 hours, which allows us of near-line process monitor of in-wafer uniformity.

A simple and common practice to evaluate Block copolymers (BCP) self-assembly performances, is on a free surface wafer. With no guiding pattern the BCP designed to form line space pattern for example, spontaneously rearranges to form a random fingerprint type of a pattern. The nature of the rearrangement is dictated by the physical properties of the BCP moieties, wafer surface treatment and the self-assembly process parameters. Traditional CDSEM metrology algorithms are designed to measure pattern with predefined structure, like linespace or oval via holes. Measurement of pattern with expected geometry can reduce measurement uncertainty. Fingerprint type of structure explored in this dissertation, poses a challenge for CD-SEM measurement uncertainty and offers an opportunity to explore 2D metrology capabilities. To measure this fingerprints we developed a new metrology approach that combines image segmentation and edge detection to measure 2D pattern with arbitrary rearrangement. The segmentation approach enabled to quantify the quality of the BCP material and process, detecting 2D attributes such as: CD and CDU at one axis, and number of intersections, length and number of PS fragments, etched PMMA spaces and donut shapes numbers on the second axis. In this paper we propose a 2D metrology to measure arbitrary BCP pattern on a free surface wafer. We demonstrate experimental results demonstrating precision data, and characterization of PS-b-PMMA BCP, intrinsic period L₀ = 38nm (Arkema), processed at different bake time and temperatures.

Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. Especially, DSA lithography using coordinated line epitaxy (COOL) process is obviously one of candidates which could be the first generation of DSA applying PS-b-PMMA block copolymer (BCP) for sub-15nm dense line patterning . DSA can enhance the pitch resolutions, and can mitigate CD errors to the values much smaller than those of the originally exposed guiding patterns. On the other hand, local line placement error often results in a worse value, with distinctive trends depending on the process conditions. To address this issue, we introduce an enhanced measurement technology of DSA line patterns with distinguishing their locations in order to evaluate nature of edge placement and roughness corresponding to individual pattern locations by using images of CD-SEM. Additionally correlations among edge roughness of each line and each space are evaluated and discussed. This method can visualize features of complicated roughness easily to control COOL process. As a result, we found the followings. (1) Line placement error and line placement roughness of DSA were slightly different each other depending on their relative position to the chemical guide patterns. (2) In middle frequency area of PSD (Power Spectral Density) analysis graphs, it was observed that shapes were sensitively changed by process conditions of chemical stripe guide size and anneals temperature. (3) Correlation coefficient analysis using PSD was able to clarify characteristics of latent defect corresponding to physical and chemical property of BCP materials.

The impact of EUV mask surface conditions on the patterned mask inspection process was investigated. The results of simulations show that the defect detection capability is degraded by the formation of a native oxide film on the surface of a Ru capped multilayer. This effect was assessed by constructing the secondary electron yield (SEY) curves of the EUV mask materials. These experimentally-obtained SEY curves were examined using semi-empirical Monte Carlo simulations. The simulation results demonstrated that a native oxide film increased the SEY, and that this effect varied with film thickness. The results suggest that defect detection capability will vary according to the thickness of the native oxide when employing an inspection system using an electron beam technique. Also of interest is the finding that the thickness of the native oxide film can be ascertained by fitting the SEY curves.

In this paper we present a new AFM based nano-patterning technique that can be used for fast defect repairing of high resolution photomasks and possibly other high-speed nano-patterning applications. The proposed method works based on hammering the sample with tapping mode AFM followed by wet cleaning of the residuals. On the area where a specific pattern should be written, the tip-sample interaction force is tuned in a controlled manner by changing the excitation frequency of the cantilever without interrupting the imaging process. Using this method several patterns where transferred to different samples with imaging speed. While the pattern was transferred to the sample in each tracing scan line, the patterned sample was imaged in retracing scan line, thus the outcome was immediately visible during the experiment.

Traditional metrology solutions face a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. With advent of advanced technology nodes and 3D processing, an increasing need is emerging for in-die metrology including across-structure and structure-to-structure characterization. A myriad of work has emerged in the past few years intending to address these challenges from various aspects; in-die OCD with reduced spot size and tilt beam on traditional critical dimension scanning electron microscopy (CDSEM) for height measurements. This paper explores the latest capability offered by PeakForce^TM Tapping Atomic Force Microscopy (PFT-AFM). The use of traditional harmonic tapping mode for scanning high aspect ratio, and complex “3D” wafer structures, results in limited depth probing capability as well as excessive tip wear. These limitations arise due to the large tip-sample interaction volume in such confined spaces. PeakForce Tapping eliminates these limitations through direct real time control of the tip-sample interaction contact force. The ability of PeakForce to measure, and respond directly to tip- sample interaction forces results in more detailed feature resolution, reduced tip wear, and improved depth capability. In this work, the PFT-AFM tool was applied for multiple applications, including the 14nm fin and replacement metal gate (RMG) applications outlined below. Results from DOE wafers, detailed measurement precision studies and correlation to reference metrology are presented for validation of this methodology. With the fin application, precision of 0.3nm is demonstrated by measuring 5 dies with 10 consecutive runs. Capability to resolve within-die and localized within-macro height variation is also demonstrated. Results obtained from the fin measurements support the increasing trend that measurements in the scribe line may not accurately represent in-die geometry, thus indicating the increasing need to measure the real device area. In-die measurement capability of peak force tapping AFM on wafers at post-poly-removal step in the RMG module is also evaluated. Precision of 1.22nm for the fin height under the gate, 1.06nm for the total gate height, and 0.77nm for the overburden are achieved in this application on a semidense structure. To the knowledge of the authors, this is the first demonstration of a robust in-die measurement of the fin height under the gate.

Nowadays most overlay metrology tools assess the overlay performance based on marker features which are deposited next to the functional device features within each layer of the semiconductor device. However, correct overlay of the relatively coarse marker features does not directly guarantee correct overlay of the much smaller device features. This paper presents the development of a tool that allows to measure the relative distance between the marker and device features within each layer of the semiconductor device, which can be used to improve the overlay at device feature level. In order to be effective, the marker to device feature distance should be measured with sub-nanometer measurement uncertainty over several millimeters range. Furthermore, the tool should be capable of profiling the marker features to allows prediction of the location interpretation of the optical diffraction based alignment sensors, which are sensitive for potential asymmetry of the marker features.

To enable this, a highly stable Atomic Force Microscope system is being developed. The probe is positioned relative to the wafer with a 6DOF controlled hexapod stage, which has a relatively large positioning range of 8x8mm. The position and orientation of this stage is measured relative to the wafer using 6 interferometers via a highly stable metrology frame. A tilted probe concept is utilized to allow profiling of the high aspect ratio marker and device features. Current activities are aimed at demonstrating the measurement capabilities of the developed AFM system.

With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.

High order overlay and alignment models require good coverage of overlay or alignment marks on the wafer. But dense sampling plans are not possible for throughput reasons. Therefore, sampling plan optimization has become a key issue. We analyze the different methods for sampling optimization and discuss the different knobs to fine-tune the methods to constraints of high volume manufacturing. We propose a method to judge sampling plan quality with respect to overlay performance, run-to-run stability and dispositioning criteria using a number of use cases from the most advanced lithography processes.

Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.

Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay. In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.

In this paper we discuss the mechanism by which process variations determine the overlay accuracy of optical metrology. We start by focusing on scatterometry, and showing that the underlying physics of this mechanism involves interference effects between cavity modes that travel between the upper and lower gratings in the scatterometry target. A direct result is the behavior of accuracy as a function of wavelength, and the existence of relatively well defined spectral regimes in which the overlay accuracy and process robustness degrades (`resonant regimes’). These resonances are separated by wavelength regions in which the overlay accuracy is better and independent of wavelength (we term these `flat regions’). The combination of flat and resonant regions forms a spectral signature which is unique to each overlay alignment and carries certain universal features with respect to different types of process variations. We term this signature the `landscape’, and discuss its universality. Next, we show how to characterize overlay performance with a finite set of metrics that are available on the fly, and that are derived from the angular behavior of the signal and the way it flags resonances. These metrics are used to guarantee the selection of accurate recipes and targets for the metrology tool, and for process control with the overlay tool. We end with comments on the similarity of imaging overlay to scatterometry overlay, and on the way that pupil overlay scatterometry and field overlay scatterometry differ from an accuracy perspective.

With the increase of process complexity in advanced nodes, the requirements of process robustness in overlay metrology continues to tighten. Especially with the introduction of newer materials in the film-stack along with typical stack variations (thickness, optical properties, profile asymmetry etc.), the signal formation physics in diffraction-based overlay (DBO) becomes an important aspect to apply in overlay metrology target and recipe selection.

In order to address the signal formation physics, an effort is made towards studying the swing-curve phenomena through wavelength and polarizations on production stacks using simulations as well as experimental technique using DBO. The results provide a wealth of information on target and recipe selection for robustness. Details from simulation and measurements will be reported in this technical publication.

As the scales of the semiconductor devices continue to shrink, accurate measurement and control of the overlay have been emphasized for securing more overlay margin. Conventional overlay analysis methods are based on the optical measurement of the overlay mark. However, the overlay data obtained from these optical methods cannot represent the exact misregistration between two layers at the circuit level. The overlay mismatch may arise from the size or pitch difference between the overlay mark and the real pattern. Pattern distortion, caused by CMP or etching, could be a source of the overlay mismatch as well. Another issue is the overlay variation in the real circuit pattern which varies depending on its location. The optical overlay measurement methods, such as IBO and DBO that use overlay mark on the scribeline, are not capable of defining the exact overlay values of the real circuit. Therefore, the overlay values of the real circuit need to be extracted to integrate the semiconductor device properly. The circuit level overlay measurement using CDSEM is time-consuming in extracting enough data to indicate overall trend of the chip. However DBM tool is able to derive sufficient data to display overlay tendency of the real circuit region with high repeatability. An E-beam based DBM(Design Based Metrology) tool can be an alternative overlay measurement method.

In this paper, we are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values. We will also demonstrate the possibility to correct misregistration between two layers using the overlay data obtained from the DBM system.

Having a well designed overlay metrology target is one of the ways to improve on-product overlay performance. The traditional screening method in which multiple targets types are added to successive reticle tape outs and then evaluated by trial-and-error may not suffice for the 7nm node and beyond. For instance, although segmentation of image-based overlay target has been reported by many as a means for improving overlay measurement, we find that segmentation does not guarantee improvement. In fact it can be undesirable. Fundamental understandings of metrology and wafer process are required to properly design the targets and carefully optimize them for a given process stack involving multilevel measurement. This paper investigates the Blossom, AIM, and scatterometry targets at the FEOL, MOL, and BEOL patterning levels in 7nm node to gain knowledge needed in order to comprehensively map out the overlay target solutions for future nodes.

We present a metrology target design (MTD) framework based on co-optimizing lithography and metrology performance. The overlay metrology performance is strongly related to the target design and optimizing the target under different process variations in a high NA optical lithography tool and measurement conditions in a metrology tool becomes critical for sub-20nm nodes. The lithography performance can be quantified by device matching and printability metrics, while accuracy and precision metrics are used to quantify the metrology performance. Based on using these metrics, we demonstrate how the optimized target can improve target printability while maintaining the good metrology performance for rotated dipole illumination used for printing a sub-100nm diagonal feature in a memory active layer. The remaining challenges and the existing tradeoff between metrology and lithography performance are explored with the metrology target designer’s perspective. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

We demonstrate a novel method to establish a root cause for an overlay excursion using optical Scatterometry metrology. Scatterometry overlay metrology consists of four cells (two per directions) of grating on grating structures that are illuminated with a laser and diffracted orders measured in the pupil plane within a certain range of aperture. State of art algorithms permit, with symmetric considerations over the targets, to extract the overlay between the two gratings. We exploit the optical properties of the target to extract further information from the measured pupil images, particularly information that maybe related to any change in the process that may lead to an overlay excursion. Root Cause Analysis or RCA is being developed to identify different kinds of process variations (either within the wafer, or between different wafers) that may indicate overlay excursions. In this manuscript, we demonstrate a collaboration between Globalfoundries and KLA-Tencor to identify a symmetric process variation using scatterometry overlay metrology and RCA technique.

Using SEM-EDS analysis on small (< 200 nm) particles is challenging, especially on a substrate with multiple background elements present. We will show a methodology combining three techniques to get the most information out of small particles. This method combines low energy EDS with a nontraditional approach to improve statistics in EDS and elemental mapping. This methodology is required for ASML’s EUV platform, the NXE scanner to continue system improvement for a system showing already low defect count. The poor particle statistics on particle defects lead to a limited amount of particles available for diagnostics, which implies that all information on particle characteristics should be used for diagnostics.

Actinic mask inspection for EUV lithography with targeted specification of sensitivity and throughput is a big challenge and effective solutions are needed. We present a novel method for actinic mask inspection, i.e. scanning scattering contrast microscopy. In this method the EUV mask is scanned with a beam of relatively small spot size and the scattered light is recorded with a pixel detector. Since the mask layout is known, the scattering profile of a defect-free mask at the detector can be calculated. The signal between the measured and calculated signal provides the deviation between the real mask and its ideal counterpart and a signal above a certain threshold indicates the existence of a defect within the illumination area. Dynamic software filtering helps to suppress strong diffraction from defect free structures and allows registration of faint defects with high sensitivity. With the continuous scan of the whole mask area, a defect map can be obtained with high throughput. Therefore, we believe that this method has the potential of providing an effective solution for actinic mask inspection. Here we discuss the basic principles of the method, present proof-of-principle experiments, describe the basic components of a feasible stand-alone tool and present early results of the performance estimations of such a tool.

Optical Proximity Correction (OPC) has continually improved in accuracy over the years by adding more physically based models. Here, we further extend OPC modeling by adding the Analytical Linescan Model (ALM) to account for systematic biases in CD-SEM metrology. The ALM was added to a conventional OPC model calibration flow and the accuracy of the calibrated model with the ALM was compared to the standard model without the ALM using validation data. Without using any adjustable parameters in the ALM, OPC validation accuracy was improved by 5%. While very preliminary, these results give hope that modeling metrology could be an important next step in OPC model improvement.

As process window margins for cutting edge DUV lithography continue to shrink, the impact of systematic patterning defects on final yield increases. Finding process window limiting hot spot patterns and monitoring them in high volume manufacturing (HVM) is increasingly challenging with conventional methods, as the size of critical defects can be below the resolution of traditional HVM inspection tools. We utilize a previously presented computational method of finding hot spot patterns by full chip simulation and use this to guide high resolution review tools by predicting the state of the hot spots on all fields of production wafers. In experiments with a 10nm node Metal LELELE vehicle we show a 60% capture rate of after-etch defects down to 3nm in size, at specific hot spot locations. By using the lithographic focus and dose correction knobs we can reduce the number of patterning defects for this test case by ~60%.

Aberration sensitivity matching between overlay metrology targets and the device cell pattern has become a common requirement on the latest DRAM process nodes. While the extreme illumination modes used demand that the delta in aberration sensitivity must be optimized, it is effectively limited by the ability to print an optimum target that will meet detectability and accuracy requirements. Therefore, advanced OPC techniques are required to ensure printability and have optimal detectability performance while maintaining sufficient process window to avoid patterning or defectivity issues.

In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.

A method of sub-nanometer uncertainty for the 3D-profile measurement using TEM (Transmission Electron Microscope) images is proposed to standardize 3D-profile measurement through reference metrology. The proposed method has been validated for profiles of Si lines, photoresist features and advanced-FinFET (Fin-shaped Field-Effect Transistor) features in our previous investigations. However, efficiency of 3D-profile measurement using TEM is limited by measurement time including processing of the sample. In this article, we demonstrate a novel on-wafer 3D-profile metrology as "FIB-to-CDSEM method" with FIB (Focused Ion Beam) slope cut and CD-SEM (Critical Dimension Secondary Electron Microscope) measuring. Using the method, a few micrometer wide on a wafer is coated and cut by 45 degree slope using FIB tool. Then, the wafer is transferred to CD-SEM to measure the cross section image by top down CD-SEM measurement. We apply FIB-to-CDSEM method to CMOS sensor device. 3D-profile and 3D-profile parameters such as top line width and side wall angles of CMOS sensor device are evaluated. The 3D-profile parameters also are measured by TEM images as reference metrology. We compare the 3D-profile parameters by TEM method and FIB-to-CDSEM method. The average values and correlations on the wafer are agreed well between TEM and FIB-to- CDSEM methods.

28nm metal 90nm pitch is one of the most challenging processes for computational lithography due to the resolution limit of DUV scanners and the variety of designs allowed by design rules. Classical two dimensional hotspot simulations and OPC correction isn’t sufficient to obtain required process windows for mass production. This paper shows how three dimensional resist effects like top loss and line end shortening have been calibrated and used during the OPC process in order to achieve larger process window. Yield results on 28FDSOI product have been used to benchmark and validate gain between classical OPC and R3D OPC.

Electron optics can assist in the fabrication of semiconductor devices in many challenges that arise from the ongoing decrease of structure size. Examples are augmenting optical lithography by electron beam direct write strategies and high-throughput imaging of patterned structures with multiple beam electron microscopes. We use multiple beam electron microscopy to image semiconductor wafers processed by electron beam lithography.

Advanced technology nodes, 10nm and beyond, employing multi-patterning techniques for pitch reduction pose new process and metrology challenges in maintaining consistent positioning of structural features. Self-Aligned Quadruple Patterning (SAQP) process is used to create the Fins in FinFET devices with pitch values well below optical lithography limits. The SAQP process bares compounding effects from successive Reactive Ion Etch (RIE) and spacer depositions. These processes induce a shift in the pitch value from one fin compared to another neighboring fin. This is known as pitch walking. Pitch walking affects device performance as well as later processes which work on an assumption that there is consistent spacing between fins. In SAQP there are 3 pitch walking parameters of interest, each linked to specific process steps in the flow. These pitch walking parameters are difficult to discriminate at a specific process step by singular evaluation technique or even with reference metrology such as Transmission Electron Microscopy (TEM). In this paper we will utilize a virtual reference to generate a scatterometry model to measure pitch walk for SAQP process flow.

DSA lithography poses new challenges in LER/LWR metrology due to its self-organized and pitch-based nature. To cope with these challenges, a novel characterization approach with new metrics and updating the older ones is required. To this end, we focus on two specific challenges of DSA line patterns: a) the large correlations between the left and right edges of a line (line wiggling, rms(LWR)<rms(LER)) and b) the cross-line correlations, i.e. the resemblance of wiggling fluctuations of nearby lines. The first is quantified by the Line Center Roughness whose low-frequency part is related to the local placement errors of device structures. For the second, we propose the c-factor correlation function which quantifies the strength of the correlations between lines versus their horizontal distance in pitches. Also, we define roughness and uniformity parameters for the pitch changes along and across lines. The proposed characterization approach is applied to the analysis of line/space patterns obtained with the Liu-Nealey (LiNe) flow (post PMMA removal and pattern transfer) revealing the effects of pattern transfer on roughness and uniformity. Finally, we calculate the cfactor function of various Next-Generation Lithography techniques and reveal their distinct footprint on the extent of cross-line correlations.

Multi-patterning lithography at the 10-nm and 7-nm nodes is driving the allowed overlay error down to extreme low values. Advanced high order overlay correction schemes are needed to control the process variability. Additionally the increase of the number of split layers results in an exponential increase of metrology complexity of the total overlay and alignment tree. At the same time, the process stack includes more hard-mask steps and becomes more and more complex, with as consequence that the setup and verification of the overlay metrology recipe becomes more critical. All of the above require a holistic approach that addresses total overlay optimization from process design to process setup and control in volume manufacturing. In this paper we will present the holistic overlay control flow designed for 10-nm and 7-nm nodes and illustrate the achievable ultimate overlay performance for a logic and DRAM use case. As figure 1 illustrates we will explain the details of the steps in the holistic flow. Overlay accuracy is the driver for target design and metrology tool optimization like wavelength and polarization. We will show that it is essential to include processing effects like etching and CMP which can result in a physical asymmetry of the bottom grating of diffraction based overlay targets. We will introduce a new method to create a reference overlay map, based on metrology data using multiple wavelengths and polarization settings. A similar approach is developed for the wafer alignment step. The overlay fingerprint correction using linear or high order correction per exposure (CPE) has a large amount of parameters. It is critical to balance the metrology noise with the ultimate correction model and the related metrology sampling scheme. Similar approach is needed for the wafer align step. Both for overlay control as well as alignment we have developed methods which include efficient use of metrology time, available for an in the litho-cluster integrated metrology use. These methods include a novel set models that efficiently describe different process fingerprints. We will explain the methods and show the benefits for logic and DRAM use cases.

We have developed a fast three dimensional Monte-Carlo framework for the investigation of shotnoise induced side-wall roughness (SWR) formation. The calculation outline is demonstrated by an example for an exposure of a 100nm thick layer of negative tone resist (NTR) resist on top of an infinitely thick silicon substrate. We use our home built Monte-Carlo simulator for electron-matter interaction for the purpose of lithography. A pattern of an isolated line is written into the resist layer by scanning a beam with 20 keV electrons over an area of 32nm×1μm (width and length). During the exposure, we use a spot size of 20 nm, beam step size of 4nm and a Poisson distributed exposure dose of 80 μC/cm², 60 μC/cm² and 40 μC/cm². During the exposure of the sample, we record the locations of the inelastic events within the resist layer. The distribution of released acids is determined under the simplified assumption that every inelastic event corresponds to a release. We now construct a three dimensional image of the (in)solubility of the resist layer within a cuboid of 128 nm(256px) wide, 800 nm(1024px) in length and 100 nm(128px) in height. It is obtained by summing the contribution of all acids to every voxel in the three dimensional image. We have used a three dimensional Gaussian with σ_x,y,z = r_d =5nm for the diffusion of the acid. The boundary between exposed and unexposed resist is determined by a threshold. The resulting image of the (in)solubility is analyzed in different ways by considering slices and three dimensional views of the border. The average line edge roughness (LER) is obtained by calculating the standard deviation (one-sigma) of the left and right border from yz-slices. By considering all slices, ranging from the top of the resist layer to the bottom of the substrate, the average LER as a function of the depth from the top surface of the resist layer is obtained. Shotnoise effects are observed as we decrease the exposure dose. An increased effect of shotnoise is observed near the vacuum and substrate interface. One contribution relates to the actual number of acids, which due to the scattering is less near the interface than away from the interface. Another contribution stems from the fact that no acids are found on the vacuum side nor on the substrate side.

In principal, the critical dimension (CD) of Nanoimprint lithography (NIL) pattern is determined by the CD of the template pattern. Unless one template is changed to another, NIL does not have a knob for direct control of the CD, such as the exposure dose and focus in optical lithography. Alternatively, the CD would be controlled by adjusting the thickness of the residual layer underneath the NIL pattern and controlling the etching process to transfer the pattern to a substrate. Controlling the residual layer thickness (RLT) can change the etching bias, resulting in the control of the CD of etched pattern. RLT is controllable by the resist dispense condition of the inkjet. For CD control, the metrology of RLT and feedback of the results to the dispense condition are extremely important. Scatterometry is the most promising metrology for the task because it is nondestructive 3D metrology with high throughput. In this paper, we discuss how to control CD in the NIL process and propose a process control flow based on scatterometry.

In this paper, we examine the sensitivity of scatterometry for the 2D and 3D isolation mounts on the substrate by applying the PML in the RCWA method. We analyze the reflectance from the silicon and resist single mount on the silicon substrates by changing the incident beam angles. First, we show the propagation properties of the electromagnetic fields propagating for the isolation mounts on the silicon substrates. Second, we examine the oblique incident reflectances for the TE and TM waves by changing the beam sizes and wavelengths. We show the reflectance properties by changing the mount length, width and height on the Si substrates. Finally, we examine the reflectances calculated by changing the wavelength for the oblique incident beams. Then, we understand that the scatterometry observation is possible for isolation mounts.

The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.

Optical scatterometry is a model based technique, which conventionally requires minimization of a predefined least square function. This minimization relies heavily on the measurement configuration: wavelength, incident angle, azimuthal angle, and sample position, which brings up the question of how to find the configuration that maximizes measurement accuracy. We propose a general measurement configuration optimization method based on error propagation theory and singular value decomposition, by which the measurement accuracy can be approximated as a function of a Jacobian matrix with respect to the measurement configurations. Simulation and experiments for a one-dimensional trapezoidal grating establishes the feasibility of the proposed method.

Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).

Shrinking technology nodes and smaller process margins require improved photolithography overlay control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field and inter-field models and the model coefficients are sent to an advanced process control (APC) system operating in an XY Cartesian basis. Dampened overlay corrections, typically via exponentially or linearly weighted moving average in time, are then retrieved from the APC system to apply on the scanner in XY Cartesian form for subsequent lot exposure. The goal of the above method is to process lots with corrections that target the least possible overlay misregistration in steady state as well as in change point situations. In this study, we model overlay errors on product using Zernike polynomials with same fitting capability as the process of reference (POR) to represent the wafer-level terms, and use the standard Cartesian polynomials to represent the field-level terms. APC calculations for wafer-level correction are performed in Zernike basis while field-level calculations use standard XY Cartesian basis. Finally, weighted wafer-level correction terms are converted to XY Cartesian space in order to be applied on the scanner, along with field-level corrections, for future wafer exposures. Since Zernike polynomials have the property of being orthogonal in the unit disk we are able to reduce the amount of collinearity between terms and improve overlay stability. Our real time Zernike modeling and feedback evaluation was performed on a 20-lot dataset in a high volume manufacturing (HVM) environment. The measured on-product results were compared to POR and showed a 7% reduction in overlay variation including a 22% terms variation. This led to an on-product raw overlay Mean + 3Sigma X&Y improvement of 5% and resulted in 0.1% yield improvement.

We present a cost-effective focus monitoring technique based on the illumination and the target co-optimization. An advanced immersion scanner can provide the freeform illumination that enables the use of any kind of custom source shape by using a programmable array of thousands of individually adjustable micro-mirrors. Therefore, one can produce non-telecentricity using the asymmetric illumination in the scanner with the optimized focus target on the cost-effective binary OMOG mask. Then, the scanner focus variations directly translate into easily measurable overlay shifts in the printed pattern with high sensitivity (ΔShift/Δfocus = 60nm/100nm). In addition, the capability of using the freeform illumination allows us to computationally co-optimize the source and the focus target, simultaneously, generating not only vertical or horizontal shifts, but also introducing diagonal pattern shifts. The focus-induced pattern shifts can be accurately measured by standard wafer metrology tools such as CD-SEM and overlay metrology tools.

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Self-Aligned Double Patterning (SADP) is widely applied in advanced sub-4X patterning technology, especially for the 1D resolution shrinkage of memory technology. As the application of SADP makes lithography minimum pitch down to half of design pitch with the remaining spacer aside core, its alignment mark and overlay (OVL) mark have to be well-segmented to ensure enough mark contrast. In this paper, we designed two types of image-based overlay (IBO) bar in bar (BIB) OVL target: bar-segmentation and background–segmentation with different duty ratio. Based on these two designed types of marks, we focus on the OVL of 2nd photo layer to 1st SADP layer with the core removed (which means spacer grating structure remained). We studied the effect of the overlay target segmentation on the precision and robustness of wafer-level overlay performance. Different lithography processes were also studied, including single layer lithography and tri-layer lithography with planarized spacer grating structures. We found there are strong correlations between overlay measurement accuracy and background segmentation rules. The results of our study will be presented and discussed in this paper.

In advanced optical lithography the requirements of focus control continues to tighten. Usable depth of focus (DoF) is already quite low due to typical sources of focus errors, such as topography, wafer warpage and the thickness of photoresist. And now the usable DoF is further decreased by hotspots (design and imaging hotspots). All these have put extra challenges to improve focus metrology, scanner focus stability calibrations and on-product correction mechanisms.

Asymmetric focus targets are developed to address robustness in focus measurements using diffraction-based focus (DBF and μDBF) metrology. A new layout specific calibration methodology is introduced for baseline focus setup and control in order to improve scanner focus uniformity and stability using the measurements of the above mentioned asymmetric targets. A similar metrology is also used for on product focus measurements. Moreover, a few novel alternative methods are also investigated for on-product focus measurements.

Data shows good correlation between DBF and process on record (POR) method using traditional FEM. The new focus calibration demonstrated robustness, stability and speed. This technical publication will report the data from all the above activities including results from various product layers.

A new focus monitor mask having novel grating structure is proposed to measure the focus variation of the scanner. The grating pattern composes of transparent line, opaque line, π-phase shift groove and π/2 -phase shift groove with their width ratio equivalent to 1:4:1:2. By using this structure, one of the first order and one of the second order of the diffraction spectrum are eliminated. Therefore, the lithography image is formed by the interference of the zeroth order and the left positive (or negative) 1st and 2nd orders, which is more sensitive to the subtle change of focus. The basic principle and characteristic of the proposed mask is described in this paper. Simulations with the lithography simulator PROLITH shows that the monitoring accuracy is improved more than 25%, compared with the conventional phase grating focus monitor (PGFM). The novel mask proposed in our job has potential to be an efficient candidate for measuring the defocus of scanner in the immersion lithography with hyper NA.

Spacer multi patterning process continues to be a key enabler of future design shrinks in DRAM and NAND process flows. Improving Critical Dimension Uniformity (CDU) for main features remains high priority for multi patterning technology and requires improved metrology and control solutions.

In this paper Spacer Patterning Technology is evaluated using an angle resolved scatterometry tool for both intra field control of the core CD after partition etch (S1) and interfield pitch-walking control after final etch (S1-S2). The intrafield measurements were done directly on device using dense sampling. The inter-field corrections were based on sparse full wafer measurements on biased OCD targets. The CDU improvement after partition-etch was verified by direct scatterometer and CD-SEM measurement on device. The final etch performance across wafer was verified with scatterometer on OCD target.

The scatterometer metrology in combination with the control strategy demonstrated a consistent CDU improvement of core (S1) intrafield CD after partition etch between 23-39% and 47-53% on interfield pitch-walking (S1-S2) after final etch. To confirm these improvements with CD-SEM, oversampling of more than 16 times is needed compared to scatterometer.

Based on the results it is concluded that scatterometry in combination with the evaluated metrology and control strategy in principle qualifies for a spacer process CDU control loop in a manufacturing environment.

In this paper, we present a study on the overlay (OVL) shift issue in contact (CT) layer aligned to poly-silicon (short as poly) layer (prior layer) in an advanced technology node [1, 2]. We have showed the wafer level OVL AEI-ADI shift (AEI: After Etch Inspection; ADI: After Developing Inspection; AEI-ADI: AEI minus ADI). Within the shot level map, there exists a center-edge difference. The OVL focus subtraction map can well match the OVL AEI-ADI shift map. Investigation into this interesting correlation finally leads to the conclusion of PR tilt. The film stress of the thick hard mask is responsible for the PR tilt. The method of OVL focus subtraction can therefore be a powerful and convenient tool to represent the OVL mark profile. It is also important to take into account the film deposition when investigating OVL AEI-ADI shift.

As the semiconductor process technology moves into more advanced nodes, design and process induced systematic defects become increasingly significant yield limiters. Therefore, early detection of these defects is crucial. Focus Exposure Matrix (FEM) and Process Window Qualification (PWQ) are routine methods for discovering systematic patterning defects and establishing the lithography process window. These methods require the stepper to expose a reticle onto the wafer at various focus and exposure settings (also known as modulations). The wafer is subsequently inspected by a bright field, broadband plasma or an E-Beam Inspection tool using a high sensitivity inspection recipe (i.e. hot scan) that often reports a million or more defects. Analyzing this vast stream of data to identify the weak patterns and arrive at the optimal focus/exposure settings requires a significant amount of data reduction through aggressive sampling and nuisance filtering schemes. However, these schemes increase alpha risk, i.e. the probability of not catching some systematic or otherwise important defects within a modulation and thus reporting that modulation as a good condition for production wafers. In order to reduce this risk and establish a more accurate process window, we describe a technique that introduces image-and-design integration methodologies into the inspection data analysis workflow.

These image-and-design integration methodologies include contour extraction and alignment to design, contour-to-design defect detection, defective/nuisance pattern retrieval, confirmed defective/nuisance pattern overlay with inspection data, and modulation-related weak-pattern ranking. The technique we present provides greater automation, from defect detection to defective pattern retrieval to decision-making steps, that allows for statistically summarized results and increased coverage of the wafer to be achieved without an adverse impact on cycle time. Statistically summarized results, lead to objective assessments of the output; and increased coverage, in turn, leads to a more comprehensive assessment of the impact of each pattern defect and each focus/exposure modulation. Overall, this leads to a more accurate determination of the process window.

The high-NA angle-resolved scatterometer YieldStar 1250D, with a small 12x12μm² inspection area, has been used to inspect CD variation After Develop (ADI) and After Partition/Final Etch (APEI/AFEI) on various layers and features of a HVM DRAM process. During recipe set-up, CD-SEM data were used to verify full recipe quality. The high sampling density enabled by the small inspection area and high speed of the YieldStar angle-resolved scatterometer could be used to reveal various kinds of CD variations. An intra-field control-loop with scanner dose corrections was tested, using very dense ADI and APEI measurements, 400ppf, 4fields. This strategy demonstrated a 21% improvement in intra-field CDU, in line with expectations from predictions. Inter-field control loops with different strategies have been simulated for APEI CD control. To capture all variations in the inter-field fingerprints a dense sampling, 24ppf full wafer, in combination with a dynamic, context-based control strategy, appeared to be necessary. An improvement of 30% of the wafer CDU (excluding the intra-field) is feasible. For the Self-Aligned Double Patterning process, essential for the dense DRAM cells, the CD variation at APEI contributes to pitch-walking at final etch. Pitch walking is an alternating OV error, therefore these control strategies will also contribute to improvement of the OV control budget.

We demonstrate a cost-effective automated rule based sparse sampling method that can detect the spatial variation of overlay errors as well as the overlay signature of the fields. Our technique satisfies the following three rules: (i) homogeneous distribution of ~200 samples across the wafer, (ii) equal number of samples in scan up and scan down condition and (iii) equal number of sampling on each overlay marks per field. When rule based samplings are implemented on the two products, the differences between the full wafer map sampling and the rule based sampling are within 3.5 nm overlay spec with residuals M+3σ of 2.4 nm (x) and 2.43 nm (y) for Product A and 2.98 nm (x) and 3.32 nm (y) for Product B.

Overlay metrology performances highly depend on the detailed design of the measured target. Hence performing simulations is an essential tool for optimizing target design. We demonstrate for scatterometry overlay (SCOL) three key factors which enable consistency in ranking between simulated and measured metrology performance for target design. The first factor, to enable high fidelity simulations for the purpose of target design, is stack and topography verification of model inputs. We report in detail the best known film metrology methods required to achieve model integrity. The second factor is the method of calculation of metrology performance metrics based on target cell reflectivities from electro-magnetic (EM) simulations. These metrics enable ranking of different designs, and subsequent choice of the best performing designs among all simulated design options, the ranking methodology being the third factor. We apply the above steps to a specific stack, where five different designs have been considered. Simulated versus measured values are compared. A good agreement between simulation and measurement is achieved.

In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

As device geometries shrink and the number of transistors on the wafer grows, new metrology solutions are required to support the development and production of next generation structures for the 10 nm node and beyond. This paper presents an innovative probe based microscope, the Rapid Probe Microscope (RPM), which is capable of obtaining nondestructive high resolution sub-nm information in all 3 dimensions and in a vacuum environment. The RPM is a platform supporting a novel probe detection and actuation system. It enables new imaging modes which are optimized for profiling narrow high aspect ratio structures as found in semiconductor devices. Additionally, the RPM can be operated in a vacuum environment allowing in-situ hybrid metrology solutions, for example operating alongside a CD or defect review SEM. Results are presented showing the imaging of thin lines and trenches, < 20 nm in width, using both a SEM and RPM to provide complementary information about the lateral and vertical dimensions of the structures. Comparison of images collected with different probes and at different sample locations demonstrates the ability of the RPM to operate consistently with long probe life and at high speed which is required for use in the High Volume Manufacturing (HVM) environment.

In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML’s Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

Requirements for on-product overlay, focus and CD uniformity continue to tighten in order to support the demands of 10nm and 7nm nodes. This results in the need for simultaneously accurate, robust and dense metrology data as input for closed-loop control solutions thereby enabling wafer-level control and high order corrections. In addition the use of opaque materials and stringent design rules drive the need for expansion of the available measurement wavelengths and metrology target design space.

Diffraction based optical metrology has been established as the leading methodology for integrated as well as standalone optical metrology for overlay, focus and CD monitoring and control in state of the art chip manufacturing. We are presenting the new approaches to diffraction based optical metrology designed to meet the ≤10nm node challenges. These approaches have been implemented in the latest addition to the YieldStar metrology platform, the YS350E introducing a new way of acquiring and processing diffraction based metrology signals.

In this paper we will present the new detection principle and its impact on key performance characteristics of overlay and focus measurements. We will also describe the wide range of applications of a newly introduced increased measurement spot size, enabling significant improvements to accuracy and process robustness of overlay and focus measurements.

With the YS350E the optical CD measurement capability is also extended, to 10x10μm² targets. We will discuss the performance and value of small targets in after-develop and after-etch applications.

At the 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical. We establish proof off concept for ASML’s holistic lithography hot spot detection and defect monitoring flow, process window optimizer (PPWO), for a 228nm metal layer process. We demonstrate prediction and verification of defect occurrence on wafer that arise from focus variations exceeding process window margins of device hotspots. We also estimate the improvement potential if design aware scanner control was applied.

Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM’s low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn’t be properly sized by the LLS due to the very shallow depth and low light scattering. Likewise, SEM cannot be used effectively for post-inspection defect review and classification of these very shallow types of defects. To verify and obtain accurate shape and three-dimensional information of those defects, automatic defect review AFM (ADR AFM) is utilized for accurate locating and imaging of DOI. In ADR AFM, non-contact mode imaging is used for non-destructive characterization and preserving tip sharpness for data repeatability and reproducibility. Locating DOI and imaging are performed automatically with a throughput of many defects per hour. Topography images of DOI has been collected and compared with SEM images. The ADR AFM has been shown as a non-destructive metrology tool for defect review and obtaining three-dimensional topography information.

In this paper we will present the comparison study of these two methods on programmed errors of critical layers of 14nm technology node. Programmed OVL errors were made on certain fields during the exposure. Full coverage OVL measurements were performed using both IBO and DBO. Linear, HOPC and iHOPC modeling has been done from non-programmed fields. Then modeling has been subtracted from these certain programmed fields, and Reticle contribution was also calculated and subtracted. In this study, metrology measurement accuracy and stability can be feasible and more accurate OVL control is enabled by selecting better OVL measurement techniques.

We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

In recent years a great deal of effort has been expended to try and reduce the reticle ESD damage problem. Methods are almost all based on the standard principles developed for the protection of ESD sensitive electronic devices – but reticles are not the same as electronic devices. Reticles are predominantly damaged by electric field rather than the conductive transfer of static charge, and the physical mechanisms that damage reticles are different from those that damage electronic devices. This paper explains why some of the established methods for ESD prevention are not the best way to protect reticles and in some cases actually increase the risk of reticle damage. Measurements are presented showing that, contrary to the widely held opinion and current practice in semiconductor manufacturing, static dissipative plastic is not the best material to use for the construction of reticle pods. An appropriate combination of insulating material and metallic shielding is shown to provide the best electrostatic protection for reticles.

As pattern design rule of device shrinks, CD control becomes more critical and important especially for resistance devices. As CD (Critical Dimension) increases, CDU (Critical Dimension Uniformity) becomes worse generally. The question with this relationship is a starting point of our study. Mainly we focused on two points. One is which factor affects CDU. The other is whether CDU degradation with large CD happens at all cases or not. We have analyzed with simulation and experiment results about CDU with splitted mask layout CD under limited conditions such as same equipment, illumination and exposure dose. As a result, we will show the relationship between CD size and CDU.

A novel method on advanced node for IBO (Image Based Overlay) data extraction accuracy is demonstrated in this work, and here some special design in triple-AIM (Advanced Imaging Metrology) is able to realize the approach.

Since triple AIM design has 3 locations left for patterning layers insertion, a new design with 2 layers locations, location-A (inner) and location-B (middle), are generated by 1st pattering, i.e. once lithography exposure, and the 2 marks grouping are formed on dielectric through lithography and etching process with a predetermined overlay "zero offset" through original mask layout design, as illustrated in Fig. (1).

And then, as following top photo resist layer, assumed location-C (outer), lithography patterning process, PR coating, exposure and development complete, full triple-AIM patterns is generated, and 3 sets of overlay data could be obtained, A to B, C to B, C to A.

Through re-calculating the overlay raw data of current (2nd patterning layer) to previous (1st patterning layer) layer by averaging [C to B] and [C to A], then theoretically the data extraction of sites would be more accuracy, since the variation of local marks signal, induced by inline process instability, could be minimized through the raw data averaging procedure.

Moreover, from raw data [A to B], an extra monitor function for detections of the inline process variation, marks selection and recipe setting optimization could be obtained, since marks in [A] and [BB] locations are both generated in 1st patterning, and with the target "zero".

So if the raw data [A to BB] is bigger or smaller than "zero" in some degree, there should be some process issue or marks condition setting error in triple-AIM design.

The integration of on-product diffraction-based focus (DBF) capability into the majority of immersion lithography layers in leading edge logic manufacturing has enabled new applications targeted towards improving cycle time and yield. A CD-based detection method is the process of record (POR) for excursion detection. The drawback of this method is increased cycle time and limited sampling due to CD-SEM metrology capacity constraints. The DBFbased method allows the addition of focus metrology samples to the existing overlay measurements on the integrated metrology (IM) system. The result enables the addition of measured focus to the SPC system, allowing a faster excursion detection method.

For focus targeting, the current method involves using a dedicated focus-exposure matrix (FEM) on all scanners, resulting in lengthy analysis times and uncertainty in the best focus. The DBF method allows the measurement to occur on the IM system, on a regular production wafer, and at the same time as the exposure. This results in a cycle time gain as well as a less subjective determination of best focus. A third application aims to use the novel onproduct focus metrology data in order to apply per-exposure focus corrections to the scanner. These corrections are particularly effective at the edge of the wafer, where systematic layer-dependent effects can be removed using DBFbased scanner feedback.

This paper will discuss the development of a methodology to accomplish each of these applications in a high-volume production environment. The new focus metrology method, sampling schemes, feedback mechanisms and analysis methods lead to improved focus control, as well as earlier detection of failures.

Within the semiconductor lithographic process, alignment control is one of the most critical considerations. In order to realize high device performance, semiconductor technology is approaching the 10 nm design rule, which requires progressively smaller overlay budgets. Simultaneously, structures are expanding in the 3^rd dimension, thereby increasing the potential for inter-layer distortion. For these reasons, device patterning is becoming increasingly difficult as the portion of the overlay budget attributed to process-induced variation increases. After lithography, overlay gives valuable feedback to the lithography tool; however overlay measurements typically have limited density, especially at the wafer edge, due to throughput considerations. Moreover, since overlay is measured after lithography, it can only react to, but not predict the process-induced overlay.

This study is a joint investigation in a high-volume manufacturing environment of the portion of overlay associated with displacement induced by a single process across many chambers. Displacement measurements are measured by Coherent Gradient Sensing (CGS) interferometry, which generates high-density displacement maps (>3 million points on a 300 mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. The results indicate the relationship between displacement and overlay shows the ability to forecast overlay values before the lithographic process. Details of the correlation including overlay/displacement range, and lot-to-lot displacement variability are considered.

Inverse Lithography Technology (ILT) has become a viable computational lithography candidate in recent years as it can produce mask output that results in process latitude and CD control in the fab that is hard to match with conventional OPC/SRAF insertion approaches.

An approach to solving the inverse lithography problem as a nonlinear, constrained minimization problem over a domain mask pixels was suggested in the paper by Y. Granik “Fast pixel-based mask optimization for inverse lithography” in 2006. The present paper extends this method to satisfy bridging and pinching constraints imposed on print contours.

Namely, there are suggested objective functions expressing penalty for constraints violations, and their minimization with gradient descent methods is considered. This approach has been tested with an ILT-based Local Printability Enhancement (LP^TM) tool in an automated flow to eliminate hotspots that can be present on the full chip after conventional SRAF placement/OPC and has been applied in 14nm, 10nm node production, single and multiple-patterning flows.

On product wafers, scanner focus is better controlled at the wafer center than at the wafer edge. This is due, in a large part, to edge roll off effects [1]. This paper quantifies the impact of edge roll off on scanner levelling non-correctable errors and correlates this to on-product effects. The main contributors and mitigation methods are also discussed for a NXT:1950 scanner.

Inspection of EUV mask substrates and blanks is demanding. We envision this is a good target application for massively parallel Atomic Force Microscopy (AFM). We envision to do a full surface characterization of EUV masks with AFM enabling 1nm true 3D resolution over the entire surface. The limiting factor to do this is in the sensor itself: throughput is limited by the time that a cantilever needs to adjust its oscillation amplitude to the surface topography while scanning. We propose to use heavily damped cantilevers to maximize the measurement bandwidth. We show that using up to 20.000 cantilevers in parallel we can then reach a throughput of one 152×152mm² substrate per 2 days with 1nm resolution.

The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today’s manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield.

In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

One of the keys to successful mass production of sub-20nm nodes in the semiconductor industry is the development of an overlay correction strategy that can meet specifications, reduce the number of layers that require dedicated chuck overlay, and minimize measurement time. Three important aspects of this strategy are: correction per exposure (CPE), integrated metrology (IM), and the prioritization of automated correction over manual subrecipes.

The first and third aspects are accomplished through an APC system that uses measurements from production lots to generate CPE corrections that are dynamically applied to future lots. The drawback of this method is that production overlay sampling must be extremely high in order to provide the system with enough data to generate CPE. That drawback makes IM particularly difficult because of the throughput impact that can be created on expensive bottleneck photolithography process tools.

The goal is to realize the cycle time and feedback benefits of IM coupled with the enhanced overlay correction capability of automated CPE without impacting process tool throughput. This paper will discuss the development of a system that sends measured data with reduced sampling via an optimized layout to the exposure tool’s computational modelling platform to predict and create “upsampled” overlay data in a customizable output layout that is compatible with the fab user CPE APC system. The result is dynamic CPE without the burden of extensive measurement time, which leads to increased utilization of IM.

We report an optical inspection guided e-beam inspection method for inline monitoring and/or process change validation. We illustrate its advantage through the case of detection of buried voids/unlanding vias, which are identified as yield-limiting defects to cause electrical connectivity failures. We inspected a back end of line (BEOL) wafer after the copper electro plating and chemical mechanical planarization (CMP) process with bright field inspection (BFI) and employed EBI to inspect full wafer with guidance of BFI klarf file. The dark voltage contrast defects were detected and confirmed as buried voids by transmission electron microscopy (TEM).

The Rapid Nano is a particle inspection system developed by TNO for the qualification of EUV reticle handling equipment. The sensitivity of this system has been improved by model based design. Our model identified two parameters that could be tuned to be able to detect smaller particles. The first step is a multi azimuth illumination mode and the second parameter is the illumination wavelength. Here we report on the results of the Rapid Nano 4, which has both of these parameters optimized to have a sub 20 nm LSE detection limit on EUV mask blanks.

The dimensional scaling in IC manufacturing strongly drives the demands on CD and defect metrology techniques and their measurement uncertainties. Defect review has become as important as CD metrology and both of them create a new metrology paradigm because it creates a completely new need for flexible, robust and scalable metrology software. Current, software architectures and metrology algorithms are performant but it must be pushed to another higher level in order to follow roadmap speed and requirements. For example: manage defect and CD in one step algorithm, customize algorithms and outputs features for each R&D team environment, provide software update every day or every week for R&D teams in order to explore easily various development strategies. The final goal is to avoid spending hours and days to manually tune algorithm to analyze metrology data and to allow R&D teams to stay focus on their expertise. The benefits are drastic costs reduction, more efficient R&D team and better process quality.

In this paper, we propose a new generation of software platform and development infrastructure which can integrate specific metrology business modules. For example, we will show the integration of a chemistry module dedicated to electronics materials like Direct Self Assembly features. We will show a new generation of image analysis algorithms which are able to manage at the same time defect rates, images classifications, CD and roughness measurements with high throughput performances in order to be compatible with HVM. In a second part, we will assess the reliability, the customization of algorithm and the software platform capabilities to follow new specific semiconductor metrology software requirements: flexibility, robustness, high throughput and scalability. Finally, we will demonstrate how such environment has allowed a drastic reduction of data analysis cycle time.

We analyze performance of different customized models on baseliner overlay data and demonstrate the reduction in overlay residuals by ~10%. Smart Sampling sets were assessed and compared with the full wafer measurements. We found that performance of the grid can still be maintained by going to one-third of total sampling points, while reducing metrology time by 60%. We also demonstrate the feasibility of achieving time to time matching using scanner fleet manager and thus identify the tool drifts even when the tool monitoring controls are within spec limits. We also explore the scanner feedback constant variation with illumination sources.

An efficient numerical method for computing angle-resolved light scattering off periodic arrays is presented. The method combines finite-element discretization with a Schur complement solver. A significant speed-up of the computations in comparison to standard finite-element method computations is observed.

Optical critical dimension (OCD) measurement has been widely demonstrated as an essential metrology method for monitoring advanced IC process in the technology node of 90 nm and beyond. However, the rapidly shrunk critical dimensions of the semiconductor devices and the increasing complexity of the manufacturing process bring more challenges to OCD. The measurement precision of OCD technology highly relies on the optical hardware configuration, spectral types, and inherently interactions between the incidence of light and various materials with various topological structures, therefore sensitivity analysis and parameter optimization are very critical in the OCD applications. This paper presents a method for seeking the optimum sensitive measurement configuration to enhance the metrology precision and reduce the noise impact to the greatest extent. In this work, the sensitivity of different types of spectra with a series of hardware configurations of incidence angles and azimuth angles were investigated. The optimum hardware measurement configuration and spectrum parameter can be identified. The FinFET structures in the technology node of 14 nm were constructed to validate the algorithm. This method provides guidance to estimate the measurement precision before measuring actual device features and will be beneficial for OCD hardware configuration.

Overlay metrology target design is an essential step prior to performing overlay measurements. This step is done through the optimization of target parameters for a given process stack. A simulation tool is therefore used to improve measurement performances. This work shows how our Metrology Target Design (MTD) simulator helps significantly in the target design process. We show the role of film and Optical CD measurements in improving significantly the fidelity of the simulations. We demonstrate that for various target design parameters we are capable of predicting measured performance metrics by simulations and correctly rank various designs performances.

Contamination tolerances in semiconductor manufacturing processes have changed dramatically in the past two decades, reaching below 20 nm according to the guidelines of the International Technology Roadmap for Semiconductors. The move to narrower line widths drives the need for innovative filtration technologies that can achieve higher particle/contaminant removal performance resulting in cleaner process fluids. Nanoporous filter membrane metrology tools that have been the workhorse over the past decade are also now reaching limits. For example, nanoparticle (NP) challenge testing is commonly applied for assessing particle retention performance of filter membranes. Factors such as high NP size dispersity, low NP detection sensitivity, and high NP particle-filter affinity impose challenges in characterizing the next generation of nanoporous filter membranes. We report a novel bio-surrogate, 5 nm DNA-dendrimer conjugate for evaluating particle retention performance of nanoporous filter membranes. A technique capable of single molecule detection is employed to detect sparse concentration of conjugate in filter permeate, providing >1000- fold higher detection sensitivity than any existing 5 nm-sized particle enumeration technique. This bio-surrogate also offers narrow size distribution, high stability and chemical tunability. This bio-surrogate can discriminate various sub-15 nm pore-rated nanoporous filter membranes based on their particle retention performance. Due to high bio-surrogate detection sensitivity, a lower challenge concentration of bio-surrogate (as compared to other NPs of this size) can be used for filter testing, providing a better representation of customer applications. This new method should provide better understanding of the next generation filter membranes for removing defect-causing contaminants from lithography processes.

Improving wafer On Product Overlay (OPO) is becoming a major challenge in lithography, especially for multipatterning techniques like N-repetitive Litho-Etch steps (LE^N, N ≥ 2). When using different scanner settings and litho processes between inter-layer overlays, intra-field overlay control becomes more complicated. In addition to the Image Placement Error (IPE) contribution, the TWINSCAN^TM lens fingerprint in combination with the exposure settings is playing a significant role as well. Furthermore the scanner needs to deal with dynamic fingerprints caused by for instance lens and/or reticle heating.

This paper will demonstrate the complementary RegC^® and TWINSCAN^TM solution for improving the OPO by cooptimizing the correction capabilities of the individual tools, respectively. As a consequence, the systematic intra-field fingerprints can be decreased along with the overlay (OVL) error at wafer level. Furthermore, the application could be utilized for extending some of the scanner actuators ranges by inducing a pre-determined signatures. These solutions perfectly fit into the ASML Litho InSight (LIS) product in which feedforward and feedback corrections based on YieldStar overlay and other measurements are used to improve the OPO. While the TWINSCAN^TM scanner corrects for global distortions (up to third order) - scanner Correctable Errors ( CE), the RegC^® application can correct for the None Correctable Errors (NCE) by making the high frequency NCE into a CE with low frequency nature. The RegC^® induces predictable deformation elements inside the quartz (Qz) material of the reticle, and by doing so it can induce a desired pre-defined signature into the reticle. The deformation introduced by the RegC^® is optimized for the actual wafer print taking into account the scale and ortho compensation by the scanner, to correct for the systematic fingerprints and the wafer overlay. These two applications might be very powerful and could contribute to achieve a better OPO performance.

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity.

The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

As design rules for leading edge devices have shrunk to 1x nm size and below, device patterns have become sensitive to sub-10nm size defects. Additionally, defectivity and yield are now increasingly dominated by systematic patterning defects. A method for identifying and inspecting these hot spot (HS) locations is necessary for both technology development and High Volume Manufacturing (HVM). In order to achieve sufficient statistical significance across the wafer for a specific product and layer, a guided, high-speed e-beam inspection system is needed to cover a significant amount of high-volume hot spot locations for process window monitoring. In this paper, we explore the capabilities of a novel, highthroughput e-beam hot spot inspection tool, SkyScan^TM 5000, on a 10nm back-end-of-line (BEOL) wafer patterned using a triple lithography-etch process. ASML’s high-resolution, design-aware computational hot spot inspection is used to identify relevant hot spot locations, including overlay-sensitive patterns. We guide the e-beam tool to these Points of Interest (POI) and obtain experimental data from inspection of 430k wafer locations. The large amount of data allows detection of wafer-level and intra-field defect signatures for a large number of hot spot patterns.

Advancement of the next generation technology nodes and emerging memory devices demand tighter lithographic focus control. Although the leveling performance of the latest-generation scanners is state of the art, challenges remain at the wafer edge due to large process variations. There are several customer configurable leveling control options available in ASML scanners, some of which are application specific in their scope of leveling improvement. In this paper, we assess the usability of leveling non-correctable error models to identify yield limiting edge dies. We introduce a novel dies-inspec based holistic methodology for leveling optimization to guide tool users in selecting an optimal configuration of leveling options. Significant focus gain, and consequently yield gain, can be achieved with this integrated approach. The Samsung site in Hwaseong observed an improved edge focus performance in a production of a mid-end memory product layer running on an ASML NXT 1960 system. 50% improvement in focus and a 1.5%p gain in edge yield were measured with the optimized configurations.

The trend in microelectronics fabrication is to produce nano-features measuring down to 10 nm and finer. The PPT levels of organic and inorganic contaminants in the photoresist, solvent and cleaning solutions are becoming a major processing variable affecting the process capability and defectivity. The photoresist usually contains gels, metals, and particulates that could interfere with the lithography process and cause microbridging defects. Nano filters of 5 nm polypropylene, 5 nm polyethylene, and 10 nm natural nylon were used to filter propylene glycol methyl ether acetate PGMEA containing 50 ppb of Na, Mg, Al, Ca, Cr, Mn, Fe, Cu, Zn, and Pb. All filters were effective in removing trivalent Al, Cr, and Fe metals indicating the mechanism for their removal as mechanical sieving. However, the nylon was also very effective in removing the divalent metals showing adsorptive properties. Furthermore, the metal removal of the nylon membrane was studied as a function of surface chemistry. Natural and charged 40 nm nylon membranes were tested and found that charged nylon is more effective for metal removal.

In the semiconductor manufacturing process, defects often occur due to a marginal process window that affects the lithography and etch processes. These defects can result in bridging patterns and overlay issues, which consequently cause electrical shorts and partially etched vias producing electrical opens. SEM tools are used to find electrical failures through voltage contrast techniques. Manufacturers who fabricate with older process technology nodes often need to use their tool set more efficiently. This paper demonstrates an application of conventional SEM review with image to golden reference image inspection capabilities in Automatic Process Inspection (API ) mode to perform electrical inspections of die features.

This paper details how to use a SEM review tool to detect systematic electrical defects. This methodology can prove beneficial while monitoring and developing patterning techniques for a specific design rule by catching electrical shorts and opens that are more visible at a lower resolution inspection used in process monitoring. Outcomes of this effort show that conventional review SEM techniques, using known areas prone to process inconsistencies derived from features pushing the design rule, have the capability to effectively and efficiently monitor fabrication process while implemented in a production setting at process nodes between 100 to 200 nm. Using e-beam review tools offers several advantages and disadvantages. This paper demonstrates that by using a SEM review tool and selecting die locations for imaging that are more likely to fail electrically, manufacturers can use SEM automatic review capabilities more effectively and efficiently. The application developed may also be applied in fabrication facilities that have limited yield monitoring capacity.

This paper is a result of collaboration between Applied Materials and Microchip Technology Inc.

This study explores the feasibility of Automated Defect Classification (ADC) with a Surface Scanning Inspection System (SSIS). The defect classification was based upon scattering sensitivity sizing curves created via modeling of the Bidirectional Reflectance Distribution Function (BRDF). The BRDF allowed for the creation of SSIS sensitivity/sizing curves based upon the optical properties of both the filmed wafer samples and the optical architecture of the SSIS.

The elimination of Polystyrene Latex Sphere (PSL) and Silica deposition on both filmed and bare Silicon wafers prior to SSIS recipe creation and ADC creates a challenge for light scattering surface intensity based defect binning. This study explored the theoretical maximal SSIS sensitivity based on native defect recipe creation in conjunction with the maximal sensitivity derived from BRDF modeling recipe creation.

Single film and film stack wafers were inspected with recipes based upon BRDF modeling. Following SSIS recipe creation, initially targeting maximal sensitivity, selected recipes were optimized to classify defects commonly found on non-patterned wafers. The results were utilized to determine the ADC binning accuracy of the native defects and evaluate the SSIS recipe creation methodology.

A statistically valid sample of defects from the final inspection results of each SSIS recipe and filmed substrate were reviewed post SSIS ADC processing on a Defect Review Scanning Electron Microscope (SEM). Native defect images were collected from each statistically valid defect bin category/size for SEM Review.

The data collected from the Defect Review SEM was utilized to determine the statistical purity and accuracy of each SSIS defect classification bin.

This paper explores both, commercial and technical, considerations of the elimination of PSL and Silica deposition as a precursor to SSIS recipe creation targeted towards ADC. Successful integration of SSIS ADC in conjunction with recipes created via BRDF modeling has the potential to dramatically reduce the workload requirements of a Defect Review SEM and save a significant amount of capital expenditure for 450mm SSIS recipe creation.

We have developed a new focus measurement method based on analyzing SEM images that can help to control a scanner. In advanced semiconductor fabrication, rigorous focus control of the scanner has been required because focus error causes a defect. Therefore, it is essential to ensure focus error are detected at wafer fabrication. In the past, the focus has been measured using test patterns made outside of the chip by optical metrology system. Thus, present focus metrology system can’t measure the focus of an arbitrary point in the chip. The new method enables a highly precise focus measurement of the arbitrary point of the chip based on a focus plane of a reference scanner. The method estimates the focus amount by analyzing side wall shapes of circuit patterns of SEM images. Side wall shapes are quantified using multisliced contours extracted from SEM-images high accuracy. By using this method, it is possible to measure the focus of the arbitrary circuit pattern area of the chip without a test pattern. We believe the method can contribute to control the scanner and to detect hot spots which appear by focus error. This new method and the evaluation results will be presented in detail in this paper.

In phase-shifting Fizeau interferometers, phase-shift errors and multiple-beam interference are the most common sources of systematic error affecting high-precision phase measurements. Nonsinusoidal waveforms can be minimized by applying synchronous detection with more than four samples. However, when phase-shift calibration is inaccurate, these algorithms cannot eliminate the effects of nonsinusoidal characteristics. Moreover, when measuring the surface profile of highly reflective samples, the calculated phase is critically determined not only by the decrease in the fringe contrast, but also by the coupling error between the harmonics and phase-shift errors. In this study, we calculate phase errors using phase-shifting algorithms that take into account the coupling error. We show that the 4N – 3 algorithm, which consists of a polynomial window function and a discrete Fourier transform term, results in the smallest phase error. As a demonstration, the surface profile of a highly reflective silicon wafer is measured using a wavelength-tuning Fizeau interferometer and the 4N – 3 algorithm.

Advanced process photolithography masks require more and more controls for registration versus design and critical dimension uniformity (CDU). The distribution of the measurement points should be distributed all over the whole mask and may be denser in areas critical to wafer overlay requirements. This means that some, if not many, of theses controls should be made inside the customer die and may use non-dedicated patterns. It is then mandatory to access the original layout database to select patterns for the metrology process.

Finding hundreds of relevant patterns in a database containing billions of polygons may be possible, but in addition, it is mandatory to create the complete metrology job fast and reliable. Combining, on one hand, a software expertise in mask databases processing and, on the other hand, advanced skills in control and registration equipment, we have developed a Mask Dataprep Station able to select an appropriate number of measurement targets and their positions in a huge database and automatically create measurement jobs on the corresponding area on the mask for the registration metrology system. In addition, the required design clips are generated from the database in order to perform the rendering procedure on the metrology system.

This new methodology has been validated on real production line for the most advanced process. This paper presents the main challenges that we have faced, as well as some results on the global performances.

The quality of patterns printed on wafer may be attributed to factors such as process window control, pattern fidelity, overlay performance, and metrology. Each of these factors play an important role in making the process more effective by ensuring that certain design- and process-specific parameters are kept within acceptable variation. Since chip size and pattern density are increasing accordingly, in-line real time catching the in-chip weak patterns/defects per million opportunities (WP-DPMO) plays more and more significant role for product yield with high density memory. However, the current in-line inspection tools focus on single layer defect inspection, not effectively and efficiently to catch multi-layer weak patterns/defects even through voltage contrast and/or special test structure design [1]-[2]. In general, the multi-layer weak patterns/defects are escaped easily by using in-line inspection and cause ignorance of product dysfunction until off-line time-consuming final PFA/EFA will be used.

To effectively and efficiently in-line real time monitor the potential multi-layer weak patterns, we quantify the bridge electrical metric between contact and gate electrodes into CD physical metric via big data from the larger field of view (FOV: 8k x 16k with 3 nm pixel equalizes to image main field size 34 um x 34 um @ 3 nm pixel) e-beam quality image contour compared to layout GDS database (D2DB) as shown in Fig. 1. Hadoop-based distributed parallel computing is implemented to improve the performance of big data architectures, Fig. 2. Therefore, the state of art in-line real time catching in-chip potential multi-layer weak patterns can be proven and achieved by following some studying cases [3]. Therefore, manufacturing sources of variations can be partitioned to systematic and random variations by applying statistical techniques based on the big data fundamental infrastructures. After big data handling, the in-chip CD and AA variations are distinguished by their spatial correlation distance. For local variations (LV) there is no correlation, whereas for global variations (GV) the correlation distance is very large [7]-[9]. This is the first time to certificate the validation of spatial distribution from the affordable bias contour big data fundamental infrastructures. And then apply statistical techniques to dig out the variation sources. The GV come from systematic issue, which could be compensated by adaptive LT condition or OPC correction. But LV comes from random issue, which being considered as intrinsic problem such as structure, material, tool capability… etc.

In this paper studying, we can find out the advanced technology node SRAM contact CD local variation (LV) dominates in total variation, about 70%. It often plays significant in-line real time catching WP-DPMO role of the product yield loss, especially for wafer edge is the worst loss within wafer distribution and causes serious reliability concern. The major root cause of variations comes from the PR material induced burr defect (LV), the second one comes from GV enhanced wafer edge short opportunity, which being attributed to three factors, first one factor is wafer edge CD deliberated enlargement for yield improvement as shown in Fig. 10. Second factor is overlaps/AA shifts due to tool capability dealing with incoming wafer’s war page issue and optical periphery layout dependent working pitch issue as shown in Fig. 9 (1)., the last factor comes from wafer edge burr enhanced by wafer edge larger Photo Resistance (PR) spin centrifugal force.

After implementing KPIs such as GV related AA/CD indexes as shown in Fig. 9 (1) and 10, respectively, and LV related burr index as shown in Fig. 11., we can construct the parts per million (PPM) level short probability model via multi-variables regression, canonical correlation analysis and logistic transformation. The model provides prediction of PPM level electrical failure by using in-line real time physical variation analysis. However in order to achieve Total Quality Management (TQM), the adaptive Statistical Process Control (SPC) charts can be implemented to in-line real time catch PPM level product malfunction at manufacturing stage. Applying for early stage monitor likes incoming raw material, Photo Resistance (PR) … etc., the LV related burr KPI SPC charts could be a powerful quality inspection vehicle. To sum up the paper’s contributions, the state of art in-line real time catching in-chip potential multi-layer physical weak patterns can be proven and achieved effectively and efficiently to associate with PPM level product dysfunction.

Wafer leveling data are usually used inside the exposure tool for ensuring good focus, then discarded. This paper describes the implementation of a monitoring and analysis solution to download these data automatically, together with the correction profiles applied by the scanner. The resulting height maps and focus residuals form the basis for monitoring metrics tailored to catching tool and process drifts and excursions in a high-volume manufacturing (HVM) environment.

In this paper, we present four six cases to highlight the potential of the method: wafer edge monitoring, chuck drift monitoring, correlations between focus residuals and overlay errors, and pre-process monitoring by chuck fingerprint removal.

A novel classification methodology is constructed for Electron Beam (E-Beam) die-to-database (D2DB) inspection results on contact and via layers. It is a design guided defects classification flow that helps to pin-point true defects from a large amount of false alarm defects. Die-to-database E-beam inspection has remarkable features that can help find systematic defects such as Damaged Via and Missing Via; which will be reported as DVC (Dark Voltage Contrast) defects. However, the D2DB result usually reports millions of defects that lie on both ‘active via’ and ‘floating via’, the former being defects-of-interest (DOI), and the latter being of little significance. The indiscriminant mixture of DOI (on active vias) and nuisance (on floating vias) is a challenge in the use of D2DB for finding systematic via defects. We overcome this challenge by overlaying the E-beam defect location onto the design layout file (GDS or OASIS) and tracing the path of the via to determine whether or not it connects to the active or diffusion layer. Our proposed flow uses Net Tracing Classification (NTC) feature in Anchor Hotspot Solution (AHS) to classify all the reported DVC defects into different groups, according to the electrical connectivity of the contact. This classification involves multiple interconnected process layers. All the reported DVC defects will be classified into three groups: (1) Real DVC defects, in which the net traces down to active layer; (2) False DVC type 1, in which the net traces down to gate (which is always dark); (3) False DVC type 2, in which the net traces down to floating metal (which is always dark as well). This enhanced defect classification is greatly helpful in separating real DVC contact/via defects from false alarms. It has a secondary benefit of reducing the total number of defects, which is helpful for subsequent in-depth data analysis. In addition, the verified real DVC locations can be used to generate care areas for E-Beam die-to-die (D2D) inspection, which can effectively improve throughput and reduce the turn-around-time (TAT). In this paper, we will discuss a use case at the Vx layer.

Immersion technology has successfully extends the application of ArF lithography in the semiconductor. However, as we further push the k₁ factor below 0.3, the patterning fidelities degrade significantly. In this paper, a novel method to quantify the mask fidelity of complex 2D patterns is proposed. With this method, the critical dimension (CD) error of both edge placement error (EPE) and corner rounding can be well described by using 2 indices "bias" and "blur" respectively. The "bias" is defined as the CD offset between the mask and the targets, and the "blur" is a derived term that can well represent the mask rounding. These 2 indices are not only able to describe the mask quality but also able to link with model parameters that are used in optical proximity correction (OPC) and some other applications. In this paper, we demonstrate the methodology and quantify the actual mask quality on the complex and critical 2D patterning in the advanced nodes.

Most advanced wafer fabs have embraced complex pattern decoration, which creates numerous challenges during in-fab reticle qualification. These optical proximity correction (OPC) techniques create assist features that tend to be very close in size and shape to the main patterns as seen in Figure 1. A small defect on an assist feature will most likely have little or no impact on the fidelity of the wafer image, whereas the same defect on a main feature could significantly decrease device functionality. In order to properly disposition these defects, reticle inspection technicians need an efficient method that automatically separates main from assist features and predicts the resulting defect impact on the wafer image. Analysis System (ADAS) defect simulation system[1]. Up until now, using ADAS simulation was limited to engineers due to the complexity of the settings that need to be manually entered in order to create an accurate result. A single error in entering one of these values can cause erroneous results, therefore full automation is necessary. In this study, we propose a new method where all needed simulation parameters are automatically loaded into ADAS. This is accomplished in two parts. First we have created a scanner parameter database that is automatically identified from mask product and level names. Second, we automatically determine the appropriate simulation printability threshold by using a new reference image (provided by the inspection tool) that contains a known measured value of the reticle critical dimension (CD). This new method automatically loads the correct scanner conditions, sets the appropriate simulation threshold, and automatically measures the percentage of CD change caused by the defect. This streamlines qualification and reduces the number of reticles being put on hold, waiting for engineer review. We also present data showing the consistency and reliability of the new method, along with the impact on the efficiency of in-fab reticle qualification.

CD-SAXS capabilities are evaluated using a Ultra-SAXS setup allowing measurement of large reciprocal space maps with a high resolution configuration. The measured structures are: i) Tungsten lines gratings and ii) Si-ARC (Silicon Antireflective Coating) lines gratings both deposited onto a thin silicon membrane (100 nm thick). Advanced data reduction is performed thanks to reverse Monte Carlo simulations. Line period, line width, sidewall angle are extracted. Stitching effect was also detected and its period was determined. Peak broadening with peak order is discussed in terms of period dispersion and cumulative roughness. Amplitude and period of lateral roughness is also determined through complementary measurements performed at ESRF.

One requirement for advanced lithography remains suitable incoming wafer topography. We propose that local wafer flatness be visualized and quantified using the techniques developed for wafer front-surface nanotopography. This is a significant change in that existing wafer topography metrology tools do not enable our proposed approach.