Paper
25 March 2016 Focus measurement using SEM image analysis of circuit pattern
Shinichi Shinoda, Yasutaka Toyoda, Yutaka Hojo, Hitoshi Sugahara, Hiroyuki Sindo
Author Affiliations +
Abstract
We have developed a new focus measurement method based on analyzing SEM images that can help to control a scanner. In advanced semiconductor fabrication, rigorous focus control of the scanner has been required because focus error causes a defect. Therefore, it is essential to ensure focus error are detected at wafer fabrication. In the past, the focus has been measured using test patterns made outside of the chip by optical metrology system. Thus, present focus metrology system can’t measure the focus of an arbitrary point in the chip. The new method enables a highly precise focus measurement of the arbitrary point of the chip based on a focus plane of a reference scanner. The method estimates the focus amount by analyzing side wall shapes of circuit patterns of SEM images. Side wall shapes are quantified using multisliced contours extracted from SEM-images high accuracy. By using this method, it is possible to measure the focus of the arbitrary circuit pattern area of the chip without a test pattern. We believe the method can contribute to control the scanner and to detect hot spots which appear by focus error. This new method and the evaluation results will be presented in detail in this paper.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Shinichi Shinoda, Yasutaka Toyoda, Yutaka Hojo, Hitoshi Sugahara, and Hiroyuki Sindo "Focus measurement using SEM image analysis of circuit pattern", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97783K (25 March 2016); https://doi.org/10.1117/12.2229089
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CITATIONS
Cited by 2 patents.
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KEYWORDS
Scanners

Scanning electron microscopy

Image analysis

Semiconducting wafers

Shape analysis

Optical fabrication

Semiconductors

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