A physical resist shrinkage model for full-chip lithography simulations

Peng Liu; Leiwu Zheng; Maggie Ma; Qian Zhao; Yongfa Fan; Qiang Zhang; Mu Feng; Xin Guo; Tom Wallow; Keith Gronlund; Ronald Goossens; Gary Zhang; Yenwen Lu

doi:10.1117/12.2239243

25 March 2016 A physical resist shrinkage model for full-chip lithography simulations

Peng Liu, Leiwu Zheng, Maggie Ma, Qian Zhao, Yongfa Fan, Qiang Zhang, Mu Feng, Xin Guo, Tom Wallow, Keith Gronlund, Ronald Goossens, Gary Zhang, Yenwen Lu

Author Affiliations +

Proceedings Volume 9779, Advances in Patterning Materials and Processes XXXIII; 97790Y (2016) https://doi.org/10.1117/12.2239243
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.

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Peng Liu, Leiwu Zheng, Maggie Ma, Qian Zhao, Yongfa Fan, Qiang Zhang, Mu Feng, Xin Guo, Tom Wallow, Keith Gronlund, Ronald Goossens, Gary Zhang, and Yenwen Lu "A physical resist shrinkage model for full-chip lithography simulations", Proc. SPIE 9779, Advances in Patterning Materials and Processes XXXIII, 97790Y (25 March 2016); https://doi.org/10.1117/12.2239243

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