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16 March 2016 Using pattern analysis methods to do fast detection of manufacturing pattern failures
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At the advanced technology node, logic design has become extremely complex and is getting more challenging as the pattern geometry size decreases. The small sizes of layout patterns are becoming very sensitive to process variations. Meanwhile, the high pressure of yield ramp is always there due to time-to-market competition. The company that achieves patterning maturity earlier than others will have a great advantage and a better chance to realize maximum profit margins.

For debugging silicon failures, DFT diagnostics can identify which nets or cells caused the yield loss. But normally, a long time period is needed with many resources to identify which failures are due to one common layout pattern or structure. This paper will present a new yield diagnostic flow, based on preliminary EFA results, to show how pattern analysis can more efficiently detect pattern related systematic defects. Increased visibility on design pattern related failures also allows more precise yield loss estimation.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Evan Zhao, Jessie Wang, Mason Sun, Jeff Wang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, and Hua Ding "Using pattern analysis methods to do fast detection of manufacturing pattern failures", Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810Z (16 March 2016);

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