This PDF file contains the editorial “350 Years of Scientific Journals” for JM3 Vol. 14 Issue 01

This PDF file contains the editorial “Special Section Guest Editorial: Continuation of Scaling with Optical and Complementary Lithography” for JM3 Vol. 14 Issue 01

Triple patterning lithography (TPL) is one of the most promising techniques in the 14-nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, TPL with end-cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In the LELE-EC process, the first two masks are LELE type double patterning, while the third mask is used to generate the end-cuts. Although the layout decomposition problem for LELELE has been well studied in the literature, only a few attempts have been made to address the LELE-EC layout decomposition problem. We propose a comprehensive study for LELE-EC layout decomposition. Layout graph and end-cut graph are constructed to extract all the geometrical relationships of both input layout and end-cut candidates. Based on these graphs, integer linear programming is formulated to minimize the conflict and the stitch numbers. The experimental results demonstrate the effectiveness of the proposed algorithms.

As technology nodes continue to shrink, layout patterns become more sensitive to lithography processes, resulting in lithography hotspots that need to be identified and eliminated during physical verification. We propose an accurate hotspot detection approach based on principal component analysis-support vector machine classifier. Several techniques, including hierarchical data clustering, data balancing, and multilevel training, are provided to enhance the performance of the proposed approach. Our approach is accurate and more efficient than conventional time-consuming lithography simulation and provides a high flexibility for adapting to new lithography processes and rules.

Self-aligned double patterning (SADP) is popularly in production use for one-dimensional-type dense patterns with good pitch control in NAND Flash memory applications and the fin layer patterning of FinFET devices, but it is still challenging to apply SADP to two-dimensional (2-D) random metal patterns. We describe the SADP layout decomposition methods for complex 2-D layouts. The SADP for complex logic metals consists of a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in the SADP process. Our technique is validated with 22-nm node industrial standard cells and logic designs, which can be applicable to sub-10-nm node design. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2-D layouts.

An in situ aberration measurement method using a phase-shift ring mask is proposed for a lithographic projection lens whose numerical aperture is below 0.8. In this method, two-dimensional phase-shift rings are designed as the measurement mask. A linear relationship model between the intensity distribution of the lateral aerial image and the aberrations is built by principal component analysis and multivariate linear regression analyses. Compared with the principal component analysis of the aerial images (AMAI-PCA) method, in which a binary mask and through-focus aerial images are used for aberration extraction, the aerial images of the phase-shift ring mask contain more useful information, providing the possibility to eliminate the crosstalk between different kinds of aberrations. Therefore, the accuracy of the aberration measurement is improved. Simulations with the lithography simulator Dr.LiTHO showed that the accuracy is improved by 15% and five more Zernike aberrations can be measured compared with the standard AMAI-PCA. Moreover, the proposed method requires less measured aerial images and is faster than the AMAI-PCA.

As one of the critical stages of a very large scale integration fabrication process, postexposure bake (PEB) plays a crucial role in determining the final three-dimensional (3-D) profiles and lessening the standing wave effects. However, the full 3-D chemically amplified resist simulation is not widely adopted during the postlayout optimization due to the long run-time and huge memory usage. An efficient simulation method is proposed to simulate the PEB while considering standing wave effects and resolution enhancement techniques, such as source mask optimization and subresolution assist features based on the Sylvester equation and Abbe-principal component analysis method. Simulation results show that our algorithm is 20× faster than the conventional Gaussian convolution method.

For the past four decades, cost and features have driven complementary metal-oxide semiconductor (CMOS) scaling. Severe lithography and material limitations seen below the 20-nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of sub-20-nm CMOS. For affordable scaling, it is imperative to work past sub-20-nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including microarchitecture design and computer-aided design, along with circuits, layout, and process technology. Furthermore, we undertook such a holistic DTCO for all critical design elements such as embedded memory, standard cell logic, analog components, and physical synthesis in a 14-nm process. Measurements results from experimental designs in a representative 14-nm process from IBM demonstrate the efficacy of the proposed approach.

We use three-dimensional self-consistent field theory (SCFT) to study the directed self-assembly (DSA) of cylinder-forming block copolymers in a peanut-shaped (also called egg-box) prepattern. The design of the prepattern shape will target the pitch reduction of the contact holes. The idea is that the DSA of block copolymers will not only lead to reduced critical dimensions relative to the template but will also repair defects in the guiding prepatterns and produce defect-free contact holes. We also study blends of block copolymers and homopolymers with various lengths and volume fractions. Using SCFT simulations, we establish the effects of the added homopolymer on defectivity, the process window, and the properties of the formed cylinders. In an attempt to quantify the effect of thermal fluctuations on the placement of the cylinders, we resort to complex Langevin simulations and perform a stochastic sampling of the assembled morphologies.

The influence of the size or volume of the phase defect embedded in the extreme ultraviolet mask on wafer printability by scanning probe microscope (SPM) is well studied. However, only a few experimental results on the measurement accuracy of the phase defect size have been reported. Therefore, in this study, the measurement repeatability of the phase defect volume using SPM and the influence of the defect volume distribution on defect detection signal intensity (DSI) using an at-wavelength dark-field defect inspection tool were examined. A programmed phase defect mask was prepared, and a defect size measurement repeatability test was conducted using an SPM. As a result, the variation of the measured volume due to the measurement repeatability was much smaller than that of the defect-to-defect variation. This result indicates that measuring the volume of each phase defect is necessary in order to evaluate the defect detection yield using a phase defect inspection tool and wafer printability. In addition, the images of phase defects were captured using an at-wavelength dark-field inspection tool from which the defect DSIs were calculated. The DSI showed a direct correlation with the defect volume.

A small but diverse set of test patterns is essential for the optimization of lithography parameters. We selectively extract the complicated patterns that are likely to cause lithography defects from test layouts. These patterns are hierarchically classified into groups based on geometric similarity; then, a small number of patterns are chosen to represent each group. We demonstrate this approach in the synthesis of test patterns for metal layers. The total area of the resulting test patterns is only 10% of that of a set produced using a more conventional technique; the resulting hotspot library has 30% fewer patterns, and the time required to create it is cut by an order of magnitude.

We present a technique for fabricating soft-lithography molds created using an epifluorescent microscope. By focusing the UV light emitted from a Hg arc lamp, we demonstrate the ability to direct-write photoresist features with a minimum resolution of 45  μm. This resolution is satisfactory for many microfluidic applications. A major advantage of this technique is its low cost, both in terms of capital investment and on-going expenditures. Furthermore, by using a motorized stage, we can quickly fabricate a design on demand, eliminating the need, cost, and lead-time required for a photomask. With the addition of an electronic shutter, complicated separate structures can be imaged and utilized to make a wide range of microfluidic devices. We demonstrate this technique using dry-film resist due to its low cost, ease of application, and less stringent safety protocols.

We investigate the directed self-assembly (DSA) of cylinder-forming block copolymers inside cylindrical guiding templates. To complement and corroborate our experimental investigations, we use field-theoretic simulations to examine the fluctuation-induced variations in the size and position of the cylindrical microdomain that forms in the middle of the guiding hole. Our study goes beyond the usual mean-field approximation and self-consistent field theory simulations (SCFT) and incorporates the effects of thermal fluctuations in the description of the self-assembly process using complex Langevin (CL) dynamics. In addition to CL simulations, we present an efficient SCFT-based approach that can inform about the positional error of the formed cylinders. In this new scheme, an external chemical-potential field is applied to displace the inner cylinder away from its centered, lowest energy configuration. In both our experimental and modeling efforts, we focus on two wall-wetting conditions: (1) minor-block-attractive sidewalls and bottom substrates and neutral top surfaces and (2) neutral sidewalls, substrates, and top surfaces. For both cases, we explore the properties of the formed cylinders, including fluctuations in the center position and the size of the domain, for various prepattern conditions. Our results indicate robust critical dimensions (CDs) of the DSA cylinders relative to the prepattern CD, with a standard deviation <0.9  nm. Likewise, we find that the DSA cylinders are accurately registered in the center of the guiding hole, with deviations in the hole-in-hole distance on the order of ∼0.7 to 1.4 nm, translating to errors in the hole-to-hole distance of ∼1 to 2 nm.

In extreme ultraviolet (EUV) lithography, plasmas are used to generate EUV light. Unfortunately, these plasmas expel high-energy ions and neutrals which damage the collector optic used to collect and focus the EUV light. One of the main problems facing EUV source manufacturers is the necessity to mitigate this debris. A magnetic mitigation system to deflect ionic debris by use of a strong permanent magnet is proposed and investigated. A detailed computational model of magnetic mitigation is presented, and experimental results from an EUV source confirm both the correctness of the model and the viability of magnetic mitigation as a successful means of deflecting ionic debris.

The authors are expanding the capabilities of the SHARP microscope by implementing complementary imaging modes. SHARP (the SEMATECH High-NA Actinic Reticle Review Project) is an actinic, synchrotron-based microscope dedicated to extreme ultraviolet photomask research. SHARP’s programmable Fourier synthesis illuminator and its use of Fresnel zoneplate lenses as imaging optics provide a versatile framework, facilitating the implementation of diverse modes beyond conventional imaging. In addition to SHARP’s set of standard zoneplates, we have created more than 100 zoneplates for complementary imaging modes, all designed to extract additional information from photomasks, to improve navigation, and to enhance defect detection. More than 50 new zoneplates are installed in the tool; the remaining lenses are currently in production. We discuss the design and fabrication of zoneplates for complementary imaging modes and present image data, obtained using Zernike phase contrast and different implementations of differential interference contrast (DIC). First results show that Zernike phase contrast can significantly increase the signal from phase defects in SHARP image data, thus improving the sensitivity of the microscope. DIC is effective on a variety of features, including phase defects and intensity speckle from substrate and multilayer roughness. The additional imaging modes are now available to users of the SHARP microscope.

Applications in ferroelectric random access memory and superparaelectric devices require the fabrication of ferroelectric capacitors at the nanoscale that exhibit extremely small leakage currents. To systematically study the material-size dependence of ferroelectric varactor performance, arrays of parallel-plate structures have been fabricated with nanoscale dielectric diameters. Electron beam lithography and inductively coupled plasma dry etching have been used to fabricate arrays of ferroelectric varactors using top electrodes as a self-aligned etch mask. Parallel-plate test structures using RF-sputtered Ba_0.6Sr_0.4TiO₃ thin-films were used to optimize the fabrication process. Varactors with diameters down to 20 nm were successfully fabricated. Current-voltage (I-V) characteristics were measured to evaluate the significance of etch-damage and fabrication quality by ensuring low leakage currents through the structures.

Patterning imperfections in semiconductor device fabrication may either be noncritical [e.g., line edge roughness (LER)] or critical, such as defects that impact manufacturing yield. As the sizes of the pitches and linewidths decrease in lithography, detection of the optical scattering from killer defects may be obscured by the scattering from other variations, called wafer noise. Understanding and separating these optical signals are critical to reduce false positives and overlooked defects. The effects of wafer noise on defect detection are assessed using volumetric processing on both measurements and simulations with the SEMATECH 9-nm gate intentional defect array. Increases in LER in simulation lead to decreases in signal-to-noise ratios due to wafer noise. Measurement procedures illustrate the potential uses in manufacturing while illustrating challenges to be overcome for full implementation. Highly geometry-dependent, the ratio of wafer noise to defect signal should continue to be evaluated for new process architectures and production nodes.

Recently published reports in the literature for bilayer lift-off processes have described recipes for the patterning of metals that have recommended metal-ion-free developers, which do etch aluminum. We report the first measurement of the dissolution rate of a commercial lift-off resist (LOR) in a sodium-based buffered commercial developer that does not etch aluminum. We describe a reliable lift-off recipe that is safe for multiple process steps in patterning thin (<100  nm) and thick aluminum devices with micron-feature sizes. Our patterning recipe consists of an acid cleaning of the substrate, the bilayer (positive photoresist/LOR) deposition and development, the sputtering of the aluminum film along with a palladium capping layer and finally, the lift-off of the metal film by immersion in the LOR solvent. The insertion into the recipe of postexposure and sequential develop-bake-develop process steps are necessary for an acceptable undercut. Our recipe also eliminates any need for accompanying sonication during lift-off that could lead to delamination of the metal pattern from the substrate. Fine patterns were achieved for both 100-nm-thick granular aluminum/palladium bilayer bolometers and 500-nm-thick aluminum gratings with 6-μm lines and 4-μm spaces.

Diatom frustules exhibit various sophisticated shapes with highly ordered hierarchical porous nanostructures, which are promising for applications in the biomimetic fabrication of nanostructured materials. We propose a universal biopattern transfer process for the fabrication of functional micro/nanostructures using diatom frustules as the biotemplates. Porous silicon microcylinders with a thickness of 20  μm are fabricated by deep reactive ion etching of a silicon substrate, which is covered by a layer of diatom frustules. With a similar process, a fast atom beam technique is used to etch the silicon substrate and silicon nanolattices are obtained. By depositing a thin layer of gold film on the diatom bonded silicon substrate, followed by releasing the diatom frustules by diluted HF, gold nanodisks with a thickness of 30 nm are successfully fabricated. The nanodisk array arranges in diamond or radial patterns, replicating the nanostructure of diatom frustules. In addition, a parylene nanodot array is also demonstrated using this diatom-based biopattern transfer process.

A three-dimensional polydimethylsiloxane (PDMS)-based microarray was one-step fabricated by releasing from an SU-8 mold for cell trapping. A human embryonic kidney-293 cell line was cultured on the PDMS microarray. By taking advantage of the chemical nature difference between PDMS surface released from oxidized silicon and released from SU-8 substrate, cells can only grow and be attached inside the PDMS microarray after 2 days of cell culture. To investigate the substantial nature of the cell adhesion and repellency on the PDMS substrate, atomic force microscopy, contact angle, and x-ray photoelectron spectroscopy methods have been carried out to analyze the physical and chemical properties of the PDMS material surfaces under different surface treatment circumstances.

Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Based on the navigation strategy of insects utilizing the polarized skylight, an integrated polarization-dependent sensor for autonomous navigation is presented. The navigation sensor has the features of compact structure, high precision, strong robustness, and a simple manufacture technique. The sensor is composed by integrating a complementary-metal-oxide-semiconductor sensor with a multiorientation nanowire grid polarizer. By nanoimprint lithography, the multiorientation nanowire polarizer is fabricated in one step and the alignment error is eliminated. The statistical theory is added to the interval-division algorithm to calculate the polarization angle of the incident light. The laboratory and outdoor tests for the navigation sensor are implemented and the errors of the measured angle are ±0.02  deg and ±1.3  deg, respectively. The results show that the proposed sensor has potential for application in autonomous navigation.

This paper describes the architecture of microstrip (MS) interfaced packaging of a coplanar-waveguide (CPW)-based radio frequency microelectromechanical systems (RF MEMS) switch in a hermetic metal-ceramic RF package. The switch is integrated along with CPW to MS (CPW-MS) transitions within the package itself. This makes the MS interfaced packaged switch module readily mountable on MS based RF boards and subsystems. The CPW-MS transition for the package was designed as a separate off-chip entity on an alumina substrate and utilizes via hole. The integrated three-dimensional model of the package consisting of the RF MEMS switch and the transitions was simulated using high frequency structure simulator. The realized module shows an insertion loss of 0.2 and 1.1 dB at 100 MHz and 7 GHz, respectively. The measured isolation is better than 60 dB at 100 MHz and 30 dB at 7 GHz. The return loss is better than 15 dB up to 7 GHz. The estimated packaging and transitioning loss is 0.5 dB at 5 GHz. This packaging architecture is a planar solution for the MS interfaced packaging of CPW based RF MEMS switches for designers who do not have access to high-end technologies, such as zero-level packaging, through silicon via or low temperature co-fired ceramics.

We describe the fabrication process for an optically addressed adaptive optics array. The device consists of a micromirror array cascaded directly on wafer fused gallium arsenide (GaAs)-gallium phosphide (GaP) photodiodes. Optically addressing a photodiode generates a photocurrent which in turn causes a voltage drop across the cascaded mirror via an integrated thin film resistor. This architecture allows parallel optical addressing of individual elements without the need for wire bonding each pixel, which can enable higher density segmented type arrays. We first describe a fabrication process for releasing a free-standing array of low stress Si_xN micromirrors on an indium phosphide (InP) support substrate. We then present a process for transferring GaAs p-i-n photodiodes on a transparent GaP support substrate using a specially designed wafer fusion fixture. The two samples when stacked together and electrically connected via a specially formulated and patterned semiconductive SU-8 resist form the final device. We report mirror displacements of up to 500 nm using this technique while requiring an optical signal as low as 150  μW.