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24 September 2018 Edge placement error fundamentals and impact of EUV: will traditional design-rule calculations work in the era of EUV?
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Abstract
The relationship between edge placement error (EPE), semiconductor design-rule determination, and predicted yield in the era of EUV lithography is examined, starting with the basics of EPE and then building up to design-rule calculations. The EPE definitions can be used as the building blocks for design-rule equations. Next the concept of “good fields” is explored and used to predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma value design-rules need to be tested to ensure high yield. The “value” can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across-chip variation of design-rule important values needs to be tested at sigma values between seven and eight, which is much higher than the 4-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations, we examine the impact of EUV lithography on sources of variation important for design-rule calculations.
Allen H. Gabor, Andrew C. Brendler, Timothy A. Brunner, Xuemei Chen, James A. Culp, and Harry J. Levinson "Edge placement error fundamentals and impact of EUV: will traditional design-rule calculations work in the era of EUV?," Journal of Micro/Nanolithography, MEMS, and MOEMS 17(4), 041008 (24 September 2018). https://doi.org/10.1117/1.JMM.17.4.041008
Received: 24 April 2018; Accepted: 23 July 2018; Published: 24 September 2018
JOURNAL ARTICLE
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