Fabrication and electrical characterization of through-Si-via interconnect for 3-D packaging

Jae-Woong Kim; Seung-Boo Jung

doi:10.1117/1.3081417

1 January 2009 Fabrication and electrical characterization of through-Si-via interconnect for 3-D packaging

Jae-Woong Kim, Seung-Boo Jung

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 8, Issue 1, 013040 (January 2009). https://doi.org/10.1117/1.3081417

Abstract

Fabrication process of through-Si-via (TSV) interconnects and their electrical characterization method were investigated for 3-D stacked packaging. A prototype, three-layer module with a flip-chip bonding process with anisotropic conductive film (ACF) was fabricated with the process. To measure a single interconnect resistance, a Kelvin structure was designed and applied on the chip and substrate. A theoretical model to calculate the connection resistance of the 3-D TSV interconnects was also derived and used to verify the experimentally measured resistance by applying the Kelvin structure designed. Optimum conditions for the formation of through-holes with the deep reactive ion-etching process were a coil power of 200 W, cycle time of 6.5/5 s, and SF₆:C₄F₈ gas flow rate of 260:100 sccm. Pulse-reverse current provided the finest grain growth during the Cu electroplating and thus prevented the trapping of voids. The experimentally measured resistance was successfully verified by the theoretical model, and the model shows that the resistance value was mainly contributed by the ACF interconnect, not by TSVs.

©(2009) Society of Photo-Optical Instrumentation Engineers (SPIE)

Citation Download Citation

Jae-Woong Kim and Seung-Boo Jung "Fabrication and electrical characterization of through-Si-via interconnect for 3-D packaging," Journal of Micro/Nanolithography, MEMS, and MOEMS 8(1), 013040 (1 January 2009). https://doi.org/10.1117/1.3081417

Published: 1 January 2009

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