This PDF file contains the editorial “Editorial: Can MEMS Take Advantage of Advances in Semiconductor Lithography?” for JM3 Vol. 9 Issue 01

As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 µm2 and other critical features across the chip with a process window are demonstrated.

We employ a direct analysis of the intensity and the phase of the diffracted light by rigorous electromagnetic field (EMF) simulations to investigate mask-induced imaging artifacts in EUV lithography. Analysis of the diffraction efficiencies and phase differences between the diffraction orders versus mask and illumination parameters is used to explore EUV-specific imaging artifacts such as feature-orientation-dependent placement errors and feature sizes, shifts of the best focus position, process window asymmetries, and other aberration-like phenomena. The results of these simulations aim to understand the reason for these EUV-specific imaging artifacts and to devise strategies for their compensation. Finally, rigorous EMF models of light scattering from EUV masks are applied to identify ideal mask absorber stacks using global optimization techniques.

We discuss the lithographic qualification of a new type of binary mask blank consisting of an opaque layer of MoSi on a glass substrate, referred to simply as OMOG. First, OMOG lithographic performance will be compared to a previous chrome/MoSi/glass binary intensity mask (BIM) blank. Standard 70-nm chrome on class (COG) was not considered, as it failed to meet mask-making requirements. Theory and a series of simulation and experimental studies show OMOG to outperform BIM, particularly due to electromagnetic effects and optical proximity correction (OPC) predictability concerns, as OMOG behaves very similarly to the ideal thin mask approximation (TMA). A new TMA-predictability metric is defined as a means to compare mask blanks. We weigh the relative advantages and disadvantages of OMOG compared to 6% attenuated phase shifting. Although both mask blanks are likely sufficient for the 32-nm and 22-nm nodes, some differences exist and are described. Overall, however, of the blanks considered, it is concluded that OMOG provides the most robust and extendable imaging solution available for 32-nm and beyond.

Poly (dimethylsiloxane) (PDMS) is meant to be utilized for a miniaturized sensor system. However, protein and biospecies often adsorb onto a PDMS surface nonspecifically. This matter is a serious challenge in the study of miniaturized sensor systems. We provide the solution, which is a prevention technique of nonspecific adsorption onto a PDMS microchip by using a functionalized silane compound self-assembled monolayer. Two demonstrations for bacteria and explosives were examined by atomic force microscopy and x-ray photoelectron spectroscopy. It was found that 1H, 1H, 2H, 2H-Perfluorooctyltriethoxysilane self-assembled monolayer on PDMS effectively blocked the nonspecific adsorption of Escherichia coli (O157:H7) and explosives such as 2, 4, 6-trinitrotoluene and 1, 3, 5-trinitroperhydro-1,3,5-triazine (RDX, Research Department Explosive).

A series of single-component molecular resists was designed, synthesized, characterized, and patterned using 100-keV e-beam lithography. An onium salt photoacid generator-based single-component resist system (referred to here as TAS) that creates a free photoacid upon exposure is shown to produce a low line edge roughness (LER) of 3.9 nm (3σ) but was limited in resolution due to photoacid diffusion. A different single-component molecular resist (referred to here as NBB) with a covalently bound nonionic photoacid generator, i.e., one in which the photoacid anion is bound to the resist core, was also synthesized. NBB was found to exhibit an improved resolution of 40 nm due to reduced photoacid diffusion while maintaining a good LER and line width roughness (LWR) of 3.9 nm and 5.6 nm, respectively. Despite the small size of NBB, it was found to exhibit a glass transition temperature of 82 °C. It also showed good adhesion, formed high-quality films, and showed no dark erosion during development. These compounds demonstrate that it is possible to form single-component molecular resists using both ionic and nonionic photoacid generators and that such small molecule resists can provide all the basic requirements to serve as functional chemically amplified resists.

A 2-D kinetic Monte Carlo mesoscale model of molecular resists is developed to probe the effects of photoacid (PAG) homogeneity, specifically PAG aggregation behavior, on the resolution, sensitivity, and line-edge roughness (LER) performance of resists. The model reproduces many pattern defects that are commonly found experimentally by simply increasing the amount of PAG aggregation. The sensitivity of resists is found to change with increasing PAG aggregation in resists with low photoacid diffusivity, but remains near constant for resists with high photoacid diffusivity. Likewise, LER is found to increase with increasing PAG aggregation in resists with low photoacid diffusivity, but appears to be weakly dependent on PAG aggregation when the resist has high photoacid diffusivity. Increasing PAG aggregation limits the absolute resolution of a resist, because there exists a trade-off between the ability of photoacid diffusion to smooth out the inhomogeneity due to PAG aggregation and the blurring of the patterned feature that reduces resolution. Even very low levels of PAG aggregation appear to greatly limit the potential of a resist for sub-30-nm resolution patterning, but increased PAG loading appears to provide a way to mitigate this problem and allow for improved absolute resolution, even in the presence of aggregation.

With regard to the resist-stacking process, it was proposed that the implantation of ions whose acceleration voltage was below 50 kV could make the lower-layer resist insoluble for the upper-layer resist-patterning process. However, the lower-layer resist pattern is observed to be removed after the upper-layer resist patterning in a pattern. In another type of a pattern, there are caves in the bottom of the lower-layer resist pattern after the upper-layer resist patterning. From the calculation of the projected range of the ions, it is found that the ions cannot reach the bottom of the lower-layer resist pattern, and therefore the bottom of the lower-layer resist is not hardened. The removal is due to the dissolution of the bottom in the lower-layer resist during the development of the upper-layer resist pattern. When the acceleration voltage of the implanted ions is set so that the projected range of the ions is larger than the resist thickness, the lower-layer resist can be made effectively insoluble for the upper-layer resist-patterning process. The ion-implanted pattern can be used as the etching mask. Moreover, the ions can be prevented from penetrating the film to be etched by adjusting the thicknesses of stacked antireflective coating.

SU-8 is a very promising material for micro-optics. It is mechanically robust with high thermal and chemical resistance, has high transmission at visible and near-infrared wavelengths, and has relatively high refractive index after curing. While lithographic processing of SU-8 is relatively common, molding of SU-8 requires different processing parameters due to challenges with solvent removal and cross-linking. Understanding the effects of the molding process on SU-8 is necessary to optimize performance of molded micro-optical components and also to enable fabrication of more complex micro-optics through subsequent lithographic processing of molded structures. We examine properties of SU-8 as it undergoes the molding process. General characterization of SU-8 shrinkage and expansion is presented, and replication of sub-100-nm structures in SU-8 is demonstrated. Solvent content and refractive index as functions of processing parameters are also examined, along with analysis of SU-8's lithographic properties after undergoing the molding process. These characterizations further enable hybrid combinations of micromolding and lithographic processing to fabricate complex 3-D micro-optics and structures that are difficult or impossible to realize using conventional techniques.

Diffractive spatial optical modulators (SOM) employing a fine-pitch pixel array were introduced. The micromechanical designs of the lead zirconate titanate (PZT) actuator and mirror ribbon structure were optimized for a small volume while maintaining the same level of performance. The same design rule and fabrication equipment were used for a new 10-µm-pitch and conventional 16-µm-pitch SOM. The optical efficiency of the new SOM was 78% (zeroth-order diffraction), which is an improvement over that of the 16-µm-pitch SOM (73%). The full on/off contrast ratio showed no differences, and a high displacement of 500 nm was achieved. The stress of the Pt/PZT/Pt actuating layer was the main parameter affecting the initial gap height and displacement of the ribbon. The required ribbon flatness could be achieved by applying a stress gradient on the SiN layer. The temperature-sensitive characteristics, which degrade image quality, could be minimized by a mechanical compensation method that takes advantage of the thermal expansion effect of Si substrates. The estimated lifetime of the device is >4000 h. The developed fine-pitch SOM device has sufficient response time and ribbon displacement to be suitable for high-quality embedded laser-projection displays. The VGA optical module was successfully demonstrated in a mobile laser projection display.

We present a 3×3 micro-optoelectromechanical systems (MOEMS) phase shifter array that achieves a λ/4 vertical displacement with peak-to-valley deformation within λ/10 (514-nm light source). The mirror reflective surface is made of an aluminum layer with a high optical reflectivity exceeding 90%. Each individual micromirror pixel is controlled and driven by comb drive actuators. The phase shifter array is fabricated using the Taiwan Semiconductor Manufacturing Company 0.35-µm 2P4M complementary metal-oxide semiconductor process. In-house post-processing is utilized to reserve a 40-µm-thick bulk-silicon under the 200 µm×200 µm mirror. This eliminates mirror deformation from residual stress after the device is released. The micromirror demonstrates a vertical displacement of λ/4 at 38 V. The device resonant frequency is 3.71 kHz, and the fill factor is 0.65. This MOEMS phase shifter array can be used as a spatial light modulator in holographic data storage systems.

Fully differential z-axis acceleration sensing often requires complicated multiwafer bonding processes. We present an integrated fully differential complementary metal-oxide semiconductor-microelectromechanical systems (CMOS-MEMS) z-axis accelerometer utilizing planar comb fingers and a pair of single-crystal silicon (SCS) torsional springs. The sidewall capacitors formed by multiple CMOS interconnect metal layers are exploited for fully differential displacement sensing with a common-centroid wiring configuration. Single crystal silicon is used throughout the device to form robust microstructures. A deep reactive ion etching (DRIE)-based microfabrication process with large processing tolerance has been developed to allow monolithic integration of CMOS circuitry with sensor structures and high fabrication yield. With an on-chip low-power, low-noise, dual-chopper amplifier that has a measured 44.5-dB gain and 1-mW power consumption, the fabricated integrated z-axis accelerometer demonstrates a sensitivity of 250 mV/g and an overall noise floor of 110 µg/√Hz.

We demonstrate a way to transport droplets by an arrowed micropillar array surface with hydrophobic parylene. The lightly hydrophilic parylene surface could be changed to hydrophobic one by treating with fluorine-based plasma (CF₄ or SF₆). The droplet on this hydrophobic parylene surface with arrowed ratchets could be transported by a speaker, and the average measured velocity was 29 mm/s. Moreover, the authors compared driving performance of the parylene surface ratchets with the ones modified by the hexamethyldisilazane (HMDS) vapor. Both the results of using hydrophobic parylene and HMDS were better than the previous work.

A prototype microelectrodischarge machine (micro-EDM) with a piezoactuated tool feed mechanism has been developed. In micro-EDM, the tool also experiences continuous wear during machining. This necessitates a tool wear compensation technique to attain a specified depth of micromachining on the workpieces. Tool wear compensation studies are performed during micromachining of silicon wafers using a copper tool. In order to estimate the necessary tool wear compensation, an axial tool wear and micromachined hole-depth measurement technique is incorporated, and variation in wear ratio at different depths of micromachining is investigated. Process simulation of micro-EDM is also performed to estimate the tool wear compensation required to reach a predefined depth during micromachining on silicon. Results obtained by simulation for the required tool feed, depth of hole achieved corresponding to a set value, and the resulting axial tool wear are in close agreement with experimental results. A machining depth variation of about 6% with respect to the estimated depth is observed. This approach provides a process control methodology for mircromachining of semiconductor and conducting materials to predefined depth with high accuracy.

Rail track geometric parameters, such as gage, level, twist, longitudinal irregularity, alignment irregularity, etc., have much influence on the operation safety of train vehicles. With the development of railway, the demand for measuring track geometric parameters precisely and efficiently has become a common concern, and to date this problem has not been properly solved. In this work, a new measurement method and a system for track geometric parameters are presented. Through analyzing advantages and disadvantages of existing measurement methods of track geometric parameters, a fiber-optic gyro is adopted for the straightness measurement. It greatly eliminates the measurement errors caused by existing methods. The feasibility of this track parameter measurement trolley is proven by practical experiments.

We investigate the effect of chip tip-to-counter electrode spacing (gap), channel-size aspect ratio, onset voltage on electrospray ionization (ESI) performance of embossed polymer microfluidic chips. Planar polymer substrates were hot embossed using an electroformed tool and a laser machined tool. The embossed microchips were tested for successful ESI demonstration with minimum sample consumption and high throughput. Factors influencing the stability of electrospray were analyzed by a series of experiments. Theoretically and experimentally, it was observed that the distance of the microchannel tip to the counter electrode directly relates to the onset voltage applied. Furthermore, the overall pattern observed is the decrease in Taylor cone size with a decrease in channel dimensions. The total ion current was analyzed as a function of time and onset voltage at various gaps. Five electrospray modes, namely, drop mode, pulse mode, Taylor-cone jet mode, multijet mode, and oscillating jet mode recorded at the open channel tips were identified and the electrospray cycle investigated. These results are in good accordance with theory, and comparisons are drawn with the findings of other researchers.

We present a novel vibration-induced electromagnetic microgenerator with enhanced power output, which uses a unique inducer made of multilayer silver (Ag) coils and a magnet with a neodymium-iron-boron (NdFeB) central core. The device converts mechanical power into electric power using electromagnetic induction that arises from relative motion between the magnet and the vibrating induction coil. The Ag coils are combined with the ceramic microspring to build the inducer. The configuration of magnets is chosen such that the magnetic field in the radial direction for electromotive force is perpendicular to the velocity vector within the vibrating induction coil. Ansoft Maxwell (Pittsburgh, Pennsylvania) modal analysis is used to predict the magnetic field. In this work, the manufacturing technology of multilayer Ag coils of low temperature cofired ceramic (LTCC) is first used and feasible for the fabrication of vibration-induced electromagnetic devices. The experimental results produce a maximum electromotive force of 25.19 mV and a power output of 1 mW at a frequency of 120 Hz and amplitude of 0.03 mm. The volumetric and mass power densities per frequency are found to be 1.97×10−2 mW/cm³·Hz and 314 mW/Kg·Hz. The new design mechanism has been build and is valid for power output.

Future lithography systems must produce more dense microchips with smaller feature sizes while maintaining throughput comparable to today's optical lithography systems. This places stringent data-handling requirements of up to 12 Tb/s on the design of any maskless lithography system. In past work, we have developed data-path architectures for such throughput and shown that lossless compression algorithms play a key role in such systems. We currently investigate the effectiveness of the Block C4 lossless layout compression algorithm in increasing throughput of direct-write maskless lithography systems. In particular, we characterize the compression efficiency of Block C4 on 1024×1024 blocks of select layers of two 65-nm chips: a state-of-the-art microprocessor chip and a low-density parity code chip used commonly in wireless communication applications. Overall, we have found that compression efficiency varies significantly from design to design, from layer to layer, and even within parts of the same layer. We propose a number of ways to cope with the variation of compression ratios within a layer and characterize the way each method affects the overall wafer layer throughput.

This PDF file contains the errata for “JM3 Vol. 9 Issue 01 Paper 3314279” for JM3 Vol. 9 Issue 01

This PDF file contains the errata for “JM3 Vol. 9 Issue 01 Paper 3322187” for JM3 Vol. 9 Issue 01