2012 is a critical year in the development of EUV lithography (EUVL) for use in high-volume manufacturing (HVM) of integrated circuits. Leading-edge semiconductor companies are manufacturing their final generation of chips using 193-nm immersion (193i) lithography with single patterning per layer.

For 32-nm half-pitch and below, EUVL can continue Moore’s law scaling of devices without resorting to double or multiple patterning using 193i lithography. Single patterning using EUVL will provide tighter overlay capability, better critical dimension uniformity, and a lower cost, but only if the light source outputs enough EUV photons per second so that the exposure tool’s cost curve as a function of wafers per hour (WPH) crosses over that of 193i lithography multiple patterning.

While the exact cost crossover point between EUVL and multiple-patterning 193i varies by product (such as DRAM and logic), WPH of $\sim 100$ should be a fair metric for gauging the success of EUVL in HVM. In the past few years, EUV source suppliers have made substantial progress through hard work, investment, and innovation. However, clean EUV power currently supports less than 10 WPH. In order to sustain Moore’s law, speedy progress in EUV source technology in the next 24 months is crucial. In addition, metrology tools for EUV masks have different requirements for EUV sources, including high brightness and low average power. Since the cost of metrology is part of the overall cost of EUVL, the throughput of metrology tools must be equally scrutinized, which again brings us to needing continuous progress in using EUV sources for metrology.

We believe now is the right time for this special section of JM³ on EUVL source technology. This edition includes:

We also believe that this special section will provide high-quality reference material that can be used to evaluate various technical options, and hopefully quicken the advance of EUV source technology.