As extreme ultraviolet (EUV) lithography approaches high-volume manufacturing (HVM) for semiconductor devices, many new challenges have emerged. To enable yield at the 7 nm and 5 nm nodes and extend EUV to the 3 nm node and beyond, multiple process, materials, and tooling challenges need to be addressed. As we continue to evaluate EUV-based processes for advanced nodes, increasing interdependence between lithography technologies, photoresist technologies, plasma etch technologies, and film stack technologies has created new opportunities in materials, integration, and the co-optimization of plasma-based patterning with lithography and process control.

To enable the implementation of EUV lithography for patterning in HVM and future nodes, challenges in multiple areas need to be addressed. These areas include imaging performance, exposure tooling improvements, EUV mask defectivity and inspection, novel stack materials, and defectivity and yield of patterning processes. Many of the papers in this special section focus on this diverse set of issues faced in EUV patterning.

One set of papers discusses issues around the image generation and lithography process for EUV applications. Erdmann et al. look at choices of absorber materials and their efficacy in mitigating three-dimensional mask effects, a very important topic as EUV technology looks to be scaled beyond the 5 nm node. Guo et al. look at the impact of sub-resolution assist features for EUV technology, which is critical to ensure the robust printing required as EUV use expands to most of the critical patterning steps. Ober et al. look to improve upon the current state-of-the-art in EUV photoresist materials as they characterize a novel set of metal-organic complexes they invented for inclusion in EUV photoresists technology.

The other set of papers focuses on the implementation of EUV technology for full wafer scale applications for HVM. De Silva et al. discuss the choices of hard mask materials and how they need to be optimized to address upstream and downstream patterning challenges. Raley et al. demonstrate structural feasibility of self-aligned block and self-aligned double patterning schemes for sub-30 nm pitch, important as the industry looks to enable the 5nm node and below. Meli et al. look at defect detection strategies and possible pathways to mitigate these issues to achieve the single-expose EUV patterning yield necessary for introduction into HVM.

In summary, this special section presents a set of papers that cover a wide range of challenges faced with the introduction of EUV lithography for aggressive patterning solutions. While the whole patterning process is extremely complex, first approaches emerge to overcome some of these issues and will enable the application of EUV-based patterning in HVM shortly. It is our intention that this collection of papers in a refereed journal will give a fair and accountable perspective on the challenges and issues faced. We would like to thank all the authors for their excellent technical submissions and thoughtful responses to the reviewers’ comments. Additionally, we’d like to thank the reviewers for their hard work and thoughtful inputs resulting in these excellent papers here. We’d also like to thank the editorial board of JM3 for giving us the opportunity to serve as guest editors for this special issue and to thank the staff of JM3 for making this special section a success.