Graphical approach for multiple values logic minimization

Abdul Ahad Sami Awwal; Khan M. Iftekharuddin

doi:10.1117/1.602123

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1 March 1999 Graphical approach for multiple values logic minimization

Abdul Ahad Sami Awwal, Khan M. Iftekharuddin

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Optical Engineering, 38(3), (1999). https://doi.org/10.1117/1.602123

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.

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Abdul Ahad Sami Awwal and Khan M. Iftekharuddin "Graphical approach for multiple values logic minimization," Optical Engineering 38(3), (1 March 1999). https://doi.org/10.1117/1.602123

Published: 1 March 1999

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