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3 April 2014 Avalanche photodiode with high responsivity in 0.35 μm CMOS
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Abstract
The presented linear mode avalanche photodiode (APD) uses the standard layers and process steps available in the 0.35-μ m Si bulk CMOS process. Due to a low-doped epitaxial layer with a resistivity of 664  Ω cm , a deep intrinsic zone is realized to enable a large depleted absorption region at already moderate bias voltages and therefore ensures a high low-voltage responsivity. In combination with avalanche gain at high bias voltages, this leads to an overall responsivity of 1.7×10 5   A/W at 1.1 nW optical input power and 670-nm wavelength. The maximum achieved avalanche gain was 4.94×10 5 . The maximum −3  dB frequency of 700 MHz was measured at a reverse bias voltage of 30 V and an optical input power of 14.7 μ W.
© 2014 Society of Photo-Optical Instrumentation Engineers (SPIE) 0091-3286/2014/$25.00 © 2014 SPIE
Wolfgang Gaberl, Kerstin Schneider-Hornstein, Reinhard Enne, and Bernhard Steindl "Avalanche photodiode with high responsivity in 0.35 μm CMOS," Optical Engineering 53(4), 043105 (3 April 2014). https://doi.org/10.1117/1.OE.53.4.043105
Published: 3 April 2014
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