Open Access
24 September 2014 Full high-definition real-time depth estimation for three-dimensional video system
Hejian Li, Ping An, Zhaoyang Zhang
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Abstract
Three-dimensional (3-D) video brings people strong visual perspective experience, but also introduces large data and complexity processing problems. The depth estimation algorithm is especially complex and it is an obstacle for real-time system implementation. Meanwhile, high-resolution depth maps are necessary to provide a good image quality on autostereoscopic displays which deliver stereo content without the need for 3-D glasses. This paper presents a hardware implementation of a full high-definition (HD) depth estimation system that is capable of processing full HD resolution images with a maximum processing speed of 125 fps and a disparity search range of 240 pixels. The proposed field-programmable gate array (FPGA)-based architecture implements a fusion strategy matching algorithm for efficiency design. The system performs with high efficiency and stability by using a full pipeline design, multiresolution processing, synchronizers which avoid clock domain crossing problems, efficient memory management, etc. The implementation can be included in the video systems for live 3-D television applications and can be used as an independent hardware module in low-power integrated applications.
CC BY: © The Authors. Published by SPIE under a Creative Commons Attribution 4.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.
Hejian Li, Ping An, and Zhaoyang Zhang "Full high-definition real-time depth estimation for three-dimensional video system," Optical Engineering 53(9), 093108 (24 September 2014). https://doi.org/10.1117/1.OE.53.9.093108
Published: 24 September 2014
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CITATIONS
Cited by 5 scholarly publications.
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KEYWORDS
Video

Field programmable gate arrays

Image processing

3D displays

Clocks

Cameras

Stereo vision systems

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