In this paper, we present the flow and results of contour-based process characterization, modeling and control used for semiconductor manufacturing. First, high-quality contours are extracted from large field of view (FOV) SEM images based on the improved Canny edge detection algorithm. Prior to the contour analysis steps, SEM image distortion correction is performed by using the loworder linear model. When there are repeating cells within one FOV, the N-sigma roughness band of the unit cell is calculated to show the stochastic process variation fingerprint. For SEM images collected from a focus-exposure matrix wafer, the contour-based process window analysis is performed to generate the depth-of-focus map for the full image, enabling precise detection of process window limiting locations. Finally, 3D compact resist models are calibrated by using both inner and outer contours from the same SEM images, which proves to be effective for the prediction of resist top loss related hotspots.
As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc) process chemical (NTD) and Control Algorithm (Focus APC) into the mature tech nodes such as 14nm/12nm, more process window and less process variations are expected for latecomer wafer fabs (Tier-2/3 companies) who just started the competition with Tier-1 companies. With improved weapons, latecomer companies are able to review their DFM strategy one more time to see whether the benefit from hardware/process/control algorithm improvement can be shared with designers In this paper, we use OPC simulation tools from different EDA suppliers to see the feasibility of transferring the benefits of hardware/process/control algorithm improvement to more relaxed design limitation through source mask optimization (SMO): 1) Better hardware: scanner (better focus/exposure variation), CMP (intrafield topo), Mask CD variation (relaxed MEEF spec), etc.; 2) New process: from positive tone development to negative tone development; 3) Better control schemes: holistic focus feedback, feedback/forward overlay control, high order CD uniformity improvement; Simulations show all those gains in hardware and process can be transferred into more relaxed design such as sub design rule structure process window include forbidden pitches (1D) and smaller E2E gaps (2D weak points).
In recent years, compact modeling of negative tone development (NTD) resists has been extensively investigated. Specific terms have been developed to address typical NTD effects, such as aerial image intensity dependent resist shrinkage and development loading. The use of photo decomposable quencher (PDQ) in NTD resists, however, brings extra challenges arising from more complicated and mixed resist effect. Due to pronounced effect of photoacid and base diffusion, the NTD resist with PDQ may exhibit opposite iso-dense bias trend compared with normal NTD resist. In this paper, we present detailed analysis of physical effects in NTD resist with PDQ, and describe respective terms to address each effect. To decouple different effects and evaluate the impact of individual terms, we identify a certain group of patterns that are most sensitive to specific resist effect, and investigate the corresponding term response. The results indicate that all the major resist effect, including PDQ-enhanced acid/base diffusion, NTD resist shrinkage and NTD development loading can be well captured by relevant terms. Based on these results, a holistic approach for the compact model calibration of NTD resist with PDQ can be established.
The resist effect may have a significant impact on source mask optimization (SMO), because the CD change in response to dose, defocus and mask size variations can be substantially modified by the resist effect. In this paper, we elaborate on how the resist effect, represented by compact resist models, changes the cost function of SMO and affects the optimized source shapes and the corresponding lithographic performance. Based on the results, we present the guidelines of using compact resist models in SMO, especially for the case of the negative tone development (NTD) process.
Line edge roughness (LER) reduction is critical during the patterning process definition and development, as the critical dimension (CD) and pitch scale in advanced semiconductor technology nodes. In this paper, we will focus on a 7nm self-aligned double patterning (SADP) process for use in back end of line (BEOL). Specifically, we will investigate LER from various lithography options and how LER changes through downstream processes, including mandrel etch, spacer deposition, hard mask open, dielectric etch and wet clean. We characterized LER as a function of several mandrel etch parameters such as O2 flow rate, over etch rate percentage and polymer deposition rates. We also characterized LER response to dielectric etch parameters and found that while some etch processes may smooth high frequency LER, there are additional cases where the final etch and wet-clean increased LER and line wiggling. Overall, we observed that lithography is the primary source of LER and we have the opportunity to reduce LER by both design and process optimization. In this paper we focused on characterization of a standard logic cell with varied CD and pitch. We looked through various designs, retargeting as well as both negative tone developer (NTD) and positive tone developer (PTD) resists for the LER reduction. We also analyzed the image log slope (ILS) of each corresponding edge and the process windows of the resist candidates. We concluded that ILS improvement and resist selection are the primary knobs to reduce LER. With optimization, we can achieve LER close to the process assumption targets for 7nm technology node. Further LER reduction techniques are definitely needed in both 7nm and future nodes even with migration from 193nm to EUV lithography.
As nodes become smaller and smaller, the OPC applied to enable these nodes becomes more and more sophisticated. This trend peaks today in curve-linear OPC approaches that are currently starting to appear on the roadmap. With this sophistication of OPC, the mask pattern complexity increases. CD-SEM based mask qualification strategies as they are used today are starting to struggle to provide a precise forecast of the printing behavior of a mask on wafer. An aerial image CD measurement performed on ZEISS Wafer-Level CD system (WLCD) is a complementary approach to mask CD-SEMs to judge the lithographical performance of the mask and its critical production features. The advantage of the aerial image is that it includes all optical effects of the mask such as OPC, SRAF, 3D mask effects, once the image is taken under scanner equivalent illumination conditions. Additionally, it reduces the feature complexity and analyzes the printing relevant CD.
State-of-the-art OPC recipes for production semiconductor manufacturing are fine-tuned, often artfully crafted parameter sets are designed to achieve design fidelity and maximum process window across the enormous variety of patterns in a given design level. In the typical technology lifecycle, the process for creating a recipe is iterative. In the initial stages, very little to no “real” design content is available for testing. Therefore, an engineer may start with the recipe from a previous node; adjust it based on known ground rules and a few test patterns and/or scaled designs, and then refine it based on hardware results. As the technology matures, more design content becomes available to refine the recipe, but it becomes more difficult to make major changes without significantly impacting the overall technology scope and schedule. The dearth of early design information is a major risk factor: unforeseen patterning difficulties (e.g. due to holes in design rules) are costly when caught late.
To mitigate this risk, we propose an automated flow that is capable of producing large-scale realistic design content, and then optimizing the OPC recipe parameters to maximize the process window for this layout. The flow was tested with a triple-patterned 10nm node 1X metal level. First, design-rule clean layouts were produced with a tool called Layout Schema Generator (LSG). Next, the OPC recipe was optimized on these layouts, with a resulting reduction in the number of hotspots. For experimental validation, the layouts were placed on a test mask, and the predicted hotspots were compared with hardware data.
The appropriate representation of the photomask in the simulation of wafer lithography processes has been shown to be of vital importance for 14-nm and below . This task is difficult, since accurate optical metrology and physical metrology of the three-dimensional mask structure is not always available. OPC models for wafer patterning comprise representations of the mask, the optics, and the photoresist process. The traditional calibration of these models has involved empirical tuning of model parameters to CD-SEM data from printed photoresist patterns. Such a flow necessarily convolves the resist effects and it has been difficult to reliably obtain mask and optical parameters which are most representative of physical reality due to aliasing effects. In this work, we have undertaken to decouple the mask model from the photoresist process by use of the ZEISS Wafer-Level CD (WLCD) tool based upon aerial image metrology. By measuring the OPC test pattern mask with WLCD, the mask parameters in the OPC model can be tuned directly without interference of resist effects. This work utilized 14-nm,10-nm, and 7-nm node masks, and we demonstrate that the use of such a flow leads to the most predictive overall OPC models, and that the mask parameters resulting from this flow more closely match the expected physical values. More specifically, the mask corner rounding, sidewall angle, and bias values were tuned to the WLCD data instead of the wafer CD SEM data, and resulted in improved predictive capability of the model. Furthermore, other mask variables not traditionally tuned can be verified or tuned by matching simulation to aerial image metrology.
As technology development advances into deep-sub-wavelength nodes, multiple patterning is becoming more essential to achieve the technology shrink requirements. Recently, Optical Proximity Correction (OPC) technology has proposed simultaneous correction of multiple mask-patterns to enable multiple patterning awareness during OPC correction. This is essential to prevent inter-layer hot-spots during the final pattern transfer. In state-of-art literature, multi-layer awareness is achieved using simultaneous resist-contour simulations to predict and correct for hot-spots during mask generation. However, this approach assumes a uniform etch shrink response for all patterns independent of their proximity, which isn’t sufficient for the full prevention of inter-exposure hot-spot, for example different color space violations post etch or via coverage/enclosure post etch.
In this paper, we explain the need to include the etch component during multiple patterning OPC. We also introduce a novel approach for Etch-aware simultaneous Multiple-patterning OPC, where we calibrate and verify a lumped model that includes the combined resist and etch responses. Adding this extra simulation condition during OPC is suitable for full chip processing from a computation intensity point of view. Also, using this model during OPC to predict and correct inter-exposures hot-spots is similar to previously proposed multiple-patterning OPC, yet our proposed approach more accurately corrects post-etch defects too.
Source Mask Optimization (SMO) has played an important role in technology setup and ground rule definition since the 2x nm technology node. While improvements in SMO algorithms have produced higher quality and more consistent results, the accuracy of the overall solution is critically linked to how faithfully the entire patterning system is modeled, from mask down to substrate. Fortunately, modeling technology has continued to advance to provide greater accuracy in modeling 3D mask effects, 3D resist behavior, and resist phenomena. Specifically, the Domain Decomposition Method (DDM) approximates the 3D mask response as a superposition of edge-responses.1 The DDM can be applied to a sectorized illumination source based on Hybrid-Hopkins Abbe approximation,2 which provides an accurate and fast solution for the modeling of 3D mask effects and has been widely used in OPC modeling. The implementation of DDM in the SMO flow, however, is more challenging because the shape and intensity of the source, unlike the case in OPC modeling, is evolving along the optimization path. As a result, it gets more complicated. It is accepted that inadequate pupil sectorization results in reduced accuracy in any application, however in SMO the required uniformity and density of pupil sampling is higher than typical OPC and modeling cases. In this paper, we describe a novel method to implement DDM in the SMO flow. The source sectorization is defined by following the universal pixel sizes used in SMO. Fast algorithms are developed to enable computation of edge signals from each fine pixel of the source. In this case, each pixel has accurate information to describe its contribution to imaging and the overall objective function. A more continuous angular spectrum from 3D mask scattering is thus captured, leading to accurate modeling of 3D mask effects throughout source optimization. This method is applied on a 2x nm middle-of-line layer test case. The impact of the 3D mask model accuracy on the source profile and corresponding lithographic performance is studied in detail. Furthermore, the impact of using a compact resist model in SMO is also investigated by using the same test case.
In this paper, we present the approach and results of layer-aware source mask target optimization. In this approach, the design target is co-optimized during source mask optimization (SMO) by considering inter-layer constraints. We tested the method on a 2x nm node metal layer by using both standard and customized cost functions for source optimization. Variable targets were defined for two process window limiting critical pattern cells, with contact-to-metal and metal-tovia coverage rules taken into consideration. The results indicate that layer-aware source mask target optimization gives consistent process window improvement over conventional SMO. The optimized targets prove to be a good balance between lithography process window and post-etch inter-layer coverage margin.
With the introduction of negative tone develop (NTD) resists to production lithography nodes, multiple NTD resist modeling challenges have surpassed the accuracy limits of the existing modeling infrastructure developed for the positive polarity process. We report the evaluation of two NTD resist modeling algorithms. The new modeling terms represent, from the first principles, the NTD resist mechanisms of horizontal shrink and horizontal development bias. Horizontal shrink describes the impact of the physical process of out-gassing on remaining resist edge location. Horizontal development bias accounts for the differential in the peak and minimum development rate with exposure intensity observed in NTD formulations. We review specific patterning characteristics by feature type, modeling accuracy impact presented by these NTD mechanisms, and their description in our compact models (Compact Model 1, CM1). All the new terms complement the accuracy advantage observed with existing CM1 resist modeling infrastructure. The new terms were tested on various NTD layers. The results demonstrate consistent model accuracy improvement for both calibration and verification. Furthermore, typical NTD model fitting challenges, such as large SRAF-induced wafer CD jump, can be overcome by the new NTD terms. Finally, we propose a joint-tuning approach for the calibration of compact models for the NTD resist.
In this paper, we present the approach and results of resist profile aware source mask optimization (SMO). In this approach, the cost functions for optimization include the image properties calculated not only from the resist bottom image planes, but also from the top image planes. Consequently, the optimized source and mask shapes are a good balance between the process window for the bottom CD’s, and top CD control to ensure a straight resist profile favorable for the etching process. We built up the flow of resist profile aware SMO and implemented it on a 1× nm node back-end layer. Two best candidate sources, SMO1 and SMO2 were generated from the conventional SMO flow and the resist profile aware SMO flow, respectively. The simulation results indicate that a better resist profile is achieved by SMO2, although it gives rise to a relatively smaller overlapping process window evaluated at the resist bottom. Wafer data including bottom CD measurement for critical pattern clips and cross-sectional SEM images from selected patterns have shown good matching with the simulation results, indicating that resist-profile aware SMO is a feasible approach to optimize the illumination sources for a reasonable bottom CD based process window as well as favorable resist profiles.
Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly
gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom
anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate
damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer
topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is
not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use
of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by
use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive