Adarsh Basavalingappa has a PhD in Nanoscale Engineering and currently works as Sr Pixel Design Engineer at Sony Electronics. Adarsh has previously worked as process engineer intern at Lam Research Corporation. He received his Master’s degree in Semiconductor Technology from Asia University, Taiwan. He has worked at Vanguard International semiconductor as ‘Device Simulation and Design Intern’ and as ‘Research Associate’ in intellectual property division of Lakshmikumaran & Sridharan. His areas of research include CMOS image sensor design, reliability of semiconductor ICs, plasma processing, EUV, and TCAD simulations.
Evaluating printability of buried native extreme ultraviolet mask phase defects through a modeling and simulation approach
Evaluating printability of buried native EUV mask phase defects through a modeling and simulation approach