Dr. Alan M. Hynes Profile

Dr. Alan M. Hynes

at Nokia Bell Labs

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Proceedings Article | 21 July 2000 Paper

Etching 200-mm diameter SCALPEL masks with the ASE process

Ian Johnston, Huma Ashraf, Jy Bhardwaj, Janet Hopkins, Alan Hynes, Glenn Nicholls, Serrita McAuley, Stephen Hall, Lilian Atabo, Gregory Bogart, Avi Kornblit, Anthony Novembre

Proceedings Volume 3997, (2000) https://doi.org/10.1117/12.390054

KEYWORDS: Etching, Semiconducting wafers, Photomasks, Silicon, Charged-particle lithography, Helium, Plasma etching, Wet etching, Plasma, Photoresist materials

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The Advanced Silicon Etch (ASE^R) process has been used for silicon substrate etching for the manufacture of SCALPEL^R (SCattering using Angular Limitation Projection E-beam Lithography) masks. The current SCALPEL^R mask fabrication process uses an aqueous solution of KOH to etch the membrane support struts in 100 mm diameter, <100> crystalline silicon wafers. This technique is undesirable for the manufacture of large diameter masks with thicker substrates, as it limits the maximum printable die size. Inductively coupled plasma (ICP) etching, using the ASE^R process, provides the only alternative etch technique. This gives support struts with vertical profiles, yielding a higher printable area than with wet etching, and is ideal for etching the substrates of large diameter masks. In addition to this, and to the benefits of dry over wet etching, the ASE^R process allows the use of wafers of any crystal orientation and gives greater flexibility in pattern placement and geometry. This paper presents process optimization data based on 200 mm diameter wafers, using a system designed specifically for this application. The key aspects of this work have focused on etch rate, CD control and uniformity enhancement. Etch rate determines the economic feasibility of this approach, particularly with etch depths of approximately 750 micrometer. Uniform etching is required to minimize the time to clear the membranes, and the CD tolerances must be met so that structural integrity is maintained. The large exposed silicon areas, (> 40% global and > 80% local), the macro loading effects caused by the edge of the pattern, and the need for near vertical strut profile, make these requirements more difficult to achieve. Etch rate and uniformity achieved, exceed the minimum specification of > 2 micrometer/min and < +/- 6% respectively.

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