As the feature sizes continue to shrink, more overlay metrology data are needed to meet
tighter overlay specifications which ensure high device yield. This study investigates the
advantages of process corrections to overlay errors using various reduced measurement
wafer schemes, and the improvement in yield that is realized using optimized overlay
correction models. The capacitor layer of a 4x node DRAM product is chosen for
verifying the sampling schemes in the experiment, because overlay errors of this layer are
sensitive to device yield. The test wafers are split into five groups; four groups are
sampled using various schemes and overlay correction models, and one group has a
programmed overlay error. The post-correction overlay residuals in full wafer, baseline
sampling and optimized sampling agree closely with predictions that are based on raw
measurements. A scheme with iHOPC (intrafield high order process correction) partial
third-order terms with a CPE (correction per exposure) function provides the best overlay
performance. The averaged device yields of reduced sampling schemes are comparable
with those of the full wafer scheme, however the reduction of the number of
measurements that is made in optimized sampling reduce the metrology tool time by 26%
from that required using the current scheme of factory. Therefore, the cost of metrology
can be further reduced by applying the proposed optimized sampling map in the routine
operations of fab.
In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer
level . This drives the need for clean metrology (resolution and precision). Results have been
published of a thorough investigation of a scatterometry-based platform from ASML , showing promising
results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6].
But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in
addition to above-mentioned need for resolution and precision, the speed and sophistication in communication
between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling
strategy for metrology plays a big role in order to achieve this.
This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization.
For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were
used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling
scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time
contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with
the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is
used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.