One of the consequences of low-k1 lithography is the discrepancy between the intended and the printed pattern, particularly in 2-D structures. Two recent technical developments offer new tools to improve manufacturing predictability, yield and control. The first enabling development provides the ability to identify the exact locations of lithography manufacturing "hot spots" using rigorous full-chip simulation. The second enabling development provides the ability to efficiently measure and characterize these critical locations on the wafer. In this study, hot spots were identified on four critical patterned layers of a 90nm-node production process using the Brion Tachyon 1100 system by comparing the design intent GDS-II database to simulated resist contours. After review and selection, the detected critical locations were sent to the Applied Materials OPC Check system. The OPC Check system created the recipes necessary to automatically drive a VeritySEM CD SEM tool to the hot spot locations on the wafer for measurements and analysis. Using the model-predicted hot spots combined with accurate wafer metrology of critical features enabled an efficient determination of the actual process window, including process-limiting features and manufacturing lithography conditions, for qualification and control of each layer.
GDSII file size is not very well correlated with the computer runtime and memory required to perform RET processing. Occasionally, small files can take many hours to process, while large files can run very quickly. The ability to accurately predict resource requirements for RET processing is essential to optimizing RET automation. In this paper, we examine GDSII complexity metrics in an effort to find a method for predicting RET processing resource requirements.
The cost of developing and deploying optical proximity correction (OPC) technology has become a non-negligible part of the total lithography cost of ownership (CoO). In this paper, we present our efforts to reduce costs associated with OPC in the development phase for the 90nm node, and production phase for the 130nm node.
The OASIS format was designed to be a replacement for the GDSII stream format. Previous papers have reported that OASIS files can be 5-20X smaller than comparable GDSII files. This paper examines the storage capabilities of OASIS, as well as other benefits, in more detail. The primary focus of this study is on OASIS integers, deltas, point-lists, and its explicit support for rectangles & squares. We also show how the two OASIS integer types and four delta types can be implemented using a single core procedure.
A shuttle mask has different chips on the same mask. The chips are not electrically connected. Alliance and foundry customers can utilize shuttle masks to share the rising cost of mask and wafer manufacturing. This paper studies the shuttle mask floorplan problem, which is formulated as a rectangle-packing problem with constraints of final die sawing strategy and die-to-die mask inspection. For our formulation, we offer a "merging" method that reduces the problem to an unconstrained slicing floorplan problem. Excellent results are obtained from the experiment with real industry data. We also study a "general" method and discuss the reason why it does not work very well.
The data volumes of individual files used in the manufacture of modern integrated circuits have become unmanageable using existing data formats specifications. The ITRS roadmap indicates that single layer MEBES files in 2002 reached the 50 GB range, worst case. Under the sponsorship of SEMI, a working group was formed to create a new format for use in describing integrated circuit layouts in a more efficient and extendible manner. This paper is a report on the status and potential benefits the new format can deliver.
The past few years have seen an explosion in the application of software techniques to improve lithographic printing. Techniques such as optical proximity correction (OPC) and phase shift masks (PSM) increase resolution and CD control by distorting the mask pattern data from the original designed pattern. These software techniques are becoming increasingly complicated and non-intuitive; and the rate of complexity increase appears to be accelerating . The benefits of these techniques to improve CD control and lower cost of ownership (COO) is balanced against the effort required to implement them and the additional problems they create.
One severe problem for users of immature and complex software tools and methodologies is quality control,  as it ultimately becomes a COO problem. Software quality can be defined very simply as the ability of an application to meet detailed customer requirements. Software quality practice can be defined as the adherence to proven methods for planning, developing, testing and maintaining software. Although software quality for lithographic resolution enhancement is extremely important, the understanding and recognition of good software development practices among lithographers is generally poor. We therefore start by reviewing the essential terms and concepts of software quality that impact lithography and COO. We then propose methods by which semiconductor process and design engineers can estimate and compare the quality of the software tools and vendors they are evaluating or using. We include examples from advanced process technology resolution enhancement work that highlight the need for high-quality software practices, and show how to avoid many problems. Note that, although several authors have worked in software application development, our analysis here is somewhat of a black box analysis. The black box is the software development organization of an RET software supplier. Our access to actual developers within these organizations is very limited. In so far as our comments with respect to the internal workings of these development organizations go, we rely on the interactions we have had with applications engineers and other technical specialists who provide our interface to the development organizations.
In this paper we introduce the concept and design of a novel phase shift mask technology, Polarized Phase Shift Mask (P:PSM). The P:PSM technology utilizes non-interference between orthogonally polarized light sources to avoid undesired destructive interference seen in conventional two-phase shift mask technology. Hence P:PSM solves the well-known 'phase edge' or 'phase conflict' problem. By obviating the 2nd exposure and 2nd mask in current Complementary Phase Shift Mask (C:PSM) technology, this single mask/single exposure technology offers significant advantages towards photolithography process as well as pattern design. We use examples of typical design and process difficulties associated with the C:PSM technology to illustrate the advantages of the P:PSM technology. We present preliminary aerial image simulation results that support the potential of this new reticle technology for enhanced design flexibility. We also propose possible mask structures and manufacturing methods for building a P:PSM.
In recent years mask data preparation (MDP) has been complicated by a number of factors, including the introduction of resolution enhancement technologies such as optical proximity correction (OPC) and phase shift masks. These complications not only have led to significant increases in file sizes and computer runtimes, but they have also created an urgent need for data management tools -- MDP automation. Current practices rely on point solutions to specific problems, such as OPC; use outdated, proprietary, non-standard, informal or inefficient data formats; and just barely manage portions of the data flow via low-level scripting. Without automation, MDP requires human intervention, which leads to longer cycle times and more errors. Without adequate data interchange formats, automation cannot succeed. This paper examines MDP processes and data formats, and suggests opportunities for improvement. Within the context of existing data formats, we examine the effect of inadequate (e.g., proprietary) data formats on MDP flow. We also examine the closest thing to an open, formal, standard data format--GDSII--and suggest improvements and even a replacement based on the extensible markup language (XML).
Although RET software technology has made great advances in recent years, very little attention has been paid to how this technology can be put into reliable and efficient use in a production environment. To stimulate EDA suppliers to take up this task, a system for not only automating RET, but also for generalizing the automation of RET is described.
It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.
Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.