As fabs transition from 200 to 300mm wafers with shrinking design rules, the risk and cost associated with overlay excursions become more severe. This significantly impacts the overall litho-cell efficiency. Effective detection, identification, and reduction of overlay excursions are essential for realizing the productivity and cost benefits of the technology shifts. We have developed a comprehensive overlay excursion management method that encompasses baseline variation analysis, statistical separation and characterization of excursion signatures and their frequencies, as well as selection of sampling plans and control methods that minimize material at risk due to excursion. A novel baseline variance estimation method is developed that takes into account the spatial signature and temporal behavior of the litho-cell overlay correction mechanisms. Spatial and temporal excursion signatures are identified and incorporated in a cost model that estimates the material at risk in an excursion cycle. The material at risk associated with various sampling plans, control charts, and cycle times is assessed considering various lot disposition and routing decisions. These results are then used in determining an optimal sampling and control strategy for effective excursion management. In this paper, we describe and demonstrate the effectiveness of the methods using actual 300mm fab overlay data from several critical layers. With a thorough assessment of the actual baseline and excursion distributions, we quantify the amount of wafer-to-wafer and within-wafer sampling necessary for detecting excursions with minimal material at risk. We also evaluate the impact of shorter cycle time and faster response to excursion, which is made possible through automation and alternative metrology configurations.
Fundamentally, advanced process control enables accelerated design-rule reduction, but simple microeconomic models that directly link the effects of advanced process control to profitability are rare or non-existent. In this work, we derive these links using a simplified model for the rate of profit generated by the semiconductor manufacturing process. We use it to explain why and how microprocessor manufacturers strive to avoid commoditization by producing only the number of dies required to satisfy the time-varying demand in each performance segment. This strategy is realized using the tactic known as speed binning, the deliberate creation of an unnatural distribution of microprocessor performance that varies according to market demand. We show that the ability of APC to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process window variation.