Semiconductor Optical Amplifiers (SOAs) are vital elements in future optical networks whether as amplifying elements to boost the optical signal. In addition to be used as amplifiers, SOAs can also be used as switching elements operating either as ON-OFF switches or as wavelength converters for wavelength routing switching. Additionally, their performance is compatible with nowadays and future transmission rates of 10, 40 and 80Gb/s and beyond. Hence, the impact they will have in all future optical networks is paramount and it is unimaginable that there will be any future optical network without them. With this knowledge a look into future optical networks reviles that the modulation format will be influenced by this development due to the physical impacts of the SOAs on the signal transmission. Hence the modulation format needs to be investigated. Here we pursue the investigation of different optical formats by means of optical simulation and do a comparison of the modulation formats with respect to the performance selected for this paper.
By eliminating optical synchronizers in optical IP routers, more complex scheduling algorithms are needed to schedule asynchronous packets. This will result in voids at the switch output thus reducing switch throughput. A novel scheduling algorithm had previously been proposed to reduce these excess losses by filling voids caused by asynchronous and variable length operation. Non-degenerate (i.e. non-uniform) buffer depth has previously been shown to improve the packet loss performance especially under bursty traffic. We investigated the performance of the void filling algorithm by combining non-degenerate and degenerate (uniform) fiber delay lines. Performance is studied for different threshold levels, i.e. the number of uniform delay lines in the feedback delay line before introducing the non-degenerate delay lines. The packet loss performance for combined non-degenerate and degenerate delay lines with void filling algorithm is presented for an optical router with a feedback delay lines buffer under self similar traffic. The recirculating delay lines buffer emulates a two-stage buffer where first stage buffers smaller packets whilst the second stage stores larger packets. This buffering mechanism is similar to SLOB (i.e. Switch With Large Optical Buffer).
A fast spectral power equalizer was designed and tested in a reconfigurable optical network testbed. Its response time is ~100 microseconds. Dynamic power fluctuation caused by add/drop switching in reconfigurable optical networks can be compensated by this technology.
A novel synchronization architecture is presented for packet based optical networks, exhibiting low insertion loss and reduced crosstalk, taking advantage of the characteristics of AWG (arrayed waveguide grating) filters. Thus far, only logarithmic delay lines have been investigated rigorously, the generic structures either based on 2 X 2 switches or on a 1-to-m splitter combined with semiconductor optical amplifier gates. The first scheme introduces not only high loss but also crosstalk, producing a high amount of interferometric noise. The latter has a lot of splitting loss to accommodate but overall, fewer stages are necessary to achieve the same delay as more than two paths per stage can be set up. In this paper, AWGs in combination with wavelength converters replace the splitter/SOA-gate geometry minimizing the optical loss, ensuring that higher levels of optical power remain to traverse the adjacent switching matrix. This novel set-up ensures that only low levels of amplification are needed minimizing concomitant noise accumulation. An incoming cell or data stream will be converted to a distinct wavelength determined by an evaluation circuit in the electronic domain. The chosen wavelength maps the input to a length of fiber which in turn represents the necessary delay, effectively executing path length (and hence time alignment) equalization of different incoming packets. Once the wavelength conversion is executed the cell is fed into an AWG, governed by a `hardwired' translation-table (input/output), ensuring cells propagate to the correct output. Finer delays are realized by cascading the principle stage.