The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient
implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the
mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture
named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results
obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion
compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long
Instruction Word (VLIW) dedicated processor.
Coarse-grained reconfigurable architectures offer high execution acceleration for code which has high instruction-level
parallelism (ILP), typically for large kernels in DSP applications. However for applications with a larger part of control
code and many smaller kernels, as present in modern video compression algorithms, the achievable acceleration through
ILP is significantly reduced. We introduce a multi-processing extension to the coarse-grained reconfigurable
architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) to deal with this kind of
applications, by enabling it to exploit thread-level parallelism (TLP). This extension consists of a partitioning of an
ADRES array into non-overlapping parts, where every partition can execute a processing thread independently, or a
processing thread can be assigned to hierarchically combined partitions which provide a larger number of resources.
Because the combining of partitions can be changed dynamically, this extension provides more flexibility than a multi-core
approach. This paper discusses the architecture and an exploration into how to potentially partition a given array
for executing an H.264/AVC baseline decoder.