Benefits of dynamic and partial reconfigurable systems are increasingly being more accepted by the industry. For this reason, SRAM-based FPGA manufacturers have improved, or even included for the first time, the support they offer for the design of this kind of systems. However, commercial tools still offer a poor flexibility, which leads to a limited efficiency. This is witnessed by the overhead introduced by the communication primitives, as well as by the inability to relocate reconfigurable modules, among others. For this reason, authors have proposed an academic design tool called DREAMS, which targets the design of dynamically reconfigurable systems. In this paper, main features offered by DREAMS are described, comparing them with existing commercial and academic tools. Moreover, a graphic user interface (GUI) is originally described in this work, with the aim of simplifying the design process, as well as to hide the low level device dependent details to the system designer. The overall goal is to increase the designer productivity. Using the graphic interface, different reconfigurable architectures are provided as design examples. Among them, both conventional slot-based architectures and mesh type designs have been included.
One of the most computational intensive tasks in recent video encoders and decoders is the deblocking filter. Its
computational complexity is considerable, and it might take more than 30% of the total computational cost of the
decoder execution. Nowadays, some of its limiting factors for reaching real-time capabilities are mainly related with
memory and speed. Trying to deal with these factors, this paper proposes a novel Deblocking filter architecture which
supports all filtering modes available in both the H.264/AVC and Scalable Video Coding (SVC) standards. It has been
implemented in a hardware scalable architecture, which benefits of the parallelism and adaptability of the algorithm and
which can be adapted dynamically in FPGAs.
Regarding to the parallelism, this architecture mapping is capable of respecting data dependencies among MBs while
several functional units (FU) are filtering data in parallel. Regarding scalability, the architecture is flexible enough for
adapting its performance to the diverse environment demands. This fact is possible by increasing or decreasing the
number of FUs, like in a systolic array. In this sense, this paper will present a composition between the FU proposed
against the state-of-the art work.
Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility
of software-based solutions combined with the performance of hardware. This combination of characteristics, together
with the development of new specific methodologies, make feasible to reach new points of the system design space, and
make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation
of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by
strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of
the device technology underneath.
In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and
low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper
from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The
first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the
embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This
reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also
described in this work, facing the interoperability problem among different families.