The high throughput time that can be achieved with laser-based lithography tools provide a tangible benefit for exposure of large areas with loose CD requirements. In this paper we present a recently developed DUV laser-based photolithography tool, supplied by Mycronic, that has been installed and qualified for optical and EUV lithography process at Intel Mask Operations. The tool utilizes a solid-state laser system for low power consumption and sustainable operation, modern electronics providing extensive logging capabilities, and an offline datapath that enables write times independent of pattern complexity. It also features multi-pass printing options that can be selected based on CD and REG requirements and throughput time, altogether providing flexibility and low cost of ownership. Tool specifications for critical dimensions and registration results will be presented in addition to tool matching and qualification data.
The wafer manufacturing industry has increased pattern complexity of the main feature and sub-resolution assist feature (SRAF) required for improving the EUV lithography process window and enabling the leading-edge technology nodes. In parallel, Inverse Lithography Technology (ILT) and its requirements of curvilinear data structure has gained momentum in recent years, putting the pressure on mask makers, in particular the mask writer. To fulfill the curvilinear feature requirements of high pattern resolution and large data volume, the mask writer needs to develop innovative techniques and update its error compensation strategies. In this paper, we will investigate the pattern resolution, local critical dimension uniformity (LCDU), and line edge roughness (LER) and explore the projected improvements in multi-beam writer technology and highlight its capability against EUV lithography requirements. We will also investigate the role of resist and process on these critical mask metrics to illustrate the overall performance against wafer requirements.
EUV mask exposure tests were conducted at Intel Mask Operation (IMO) on a MBMW201 multi-beam writer to study the effects of writing beam diameter and associate blurs, mask exposure dose, and photoresist on pattern resolution, LCDU, and LER. An analytical model was also used to predict the trend and determine the dependency of these lithographic metrics on the writer exposure conditions.
EUV lithography requirements continue to present new challenges and opportunities for multi-beam mask writer. Driven by sub-10nm node mask requirements for higher resolution, CD uniformity, pattern placement accuracy, lower line edge roughness (LER), and zero writer-induced defects, the multi-beam mask patterning technology must keep the pace, continue to innovate, and work hand-in-hand with mask makers to overcome these challenges to meet the mask and wafer manufacturing metrics and requirements.
In this paper we will review some of these challenges from the mask maker point of view. Also, we will shed light on a bigger challenge of transitioning to curvilinear mask ILT (Inverse Lithography Technology) data structure and the support needed from multi-beam writer to handle large data volume. Processing and managing this large growth of data helps the mask industry speed up the process of adapting to this technology and enabling EUV mask and wafer manufacturing reach its ultimate goals.
Multi-beam mask writers (MBMW) manufactured by IMS Nanofabrication have been increasingly been accepted into mainstream mask making. Over the past decade, this new class of tools has successfully transitioned from the concept, to development and finally to the production phase. Significant technical challenges specific to the architecture were encountered and overcome. Many of these challenges are related to the large image size used by this writer. In this paper, we will review the motivation to develop this new class of writers and the key technical challenges which had to be overcome to realize lithographic promise. Current status and future opportunities to improve the architecture will be discussed.
Mask patterning capability continues to be a key enabler for wafer patterning. Mask writer performance is critical to meet reticle resolution, critical dimension uniformity, registration, and throughput requirements. Technology trends indicate that mask requirements will require higher dose resists with more complex designs producing write time growth that significantly exceeds Moore’s law estimates. Sub 10 nm technology node requirements may exceed what is practically or economically achievable using conventional single beam writers. This is driving the need to explore alternative e-beam mask writer architectures for future nodes.
Several equipment suppliers are proposing new architectures for mask patterning. These approaches share the characteristic of some level of parallelism to solve the throughput challenge caused by increasing mask pattern complexity. Although parallelism is a proven approach in laser mask writers, it has not been integrated into an e-beam platform. All of the approaches for multibeam e-beam architectures have unique technical difficulties. In some cases, suppliers have produced proof of concept results to demonstrate the feasibility of their approach and address key technical risks. Although these results are encouraging, it is clear that they need more time and industry assistance to produce a commercially worthy mask writer.
Key drivers will be considered. Proposed evolutionary extensions of the current architecture will be evaluated. The need for revolutionary architectures to satisfy future mask patterning will be explored.
Aggressive 193nm optical lithography solutions have in turn led to increasingly complex model-based OPC methodologies. This complexity married with the inevitable march of Moore's Law has produced a figure count explosion at the mask writer level. Variable shaped beam equipment manufacturers have tried to mollify the impact of this figure count explosion on the write time by the introduction of new technologies such as increased beam current density, faster DAC amplifiers and more efficient stage algorithms. Despite these efforts, mask manufacturers continue to explore ways of increasing writer throughput and available capacity. This study models the impact of further improvements in beam current density and settling times. Furthermore, this model will be used to prescribe the necessary improvement rates needed to keep pace with the shot count trends extending beyond the 45nm node.
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