The 5nm and 7nm technology nodes will continue recent scaling trends and will deliver significantly smaller minimum features, standard cell areas and SRAM cell areas vs. the 10nm node. There are tremendous economic pressures to shrink each subsequent technology, though in a cost-effective and performance enhancing manner. IC manufacturers are eagerly awaiting EUV so that they can more aggressively shrink their technology than they could by using complicated MPT. The current 0.33NA EUV tools and processes also have their patterning limitations. EUV scanner lenses, scanner sources, masks and resists are all relatively immature compared to the current lithography manufacturing baseline of 193i. For example, lens aberrations are currently several times larger (as a function of wavelength) in EUV scanners than for 193i scanners. Robustly patterning 16nm L/S fully random logic metal patterns and 40nm pitch random logic rectangular contacts with 0.33NA EUV are tough challenges that will benefit from advanced OPC/RET. For example, if an IC manufacturer can push single exposure device layer resolution 10% tighter using improved ILT to avoid using DPT, there will be a significant cost and process complexity benefit to doing so. ILT is well known to have considerable benefits in finding flexible 193i mask pattern solutions to improve process window, improve 2D CD control, improve resolution in low K1 lithography regime and help to delay the introduction of DPT. However, ILT has not previously been applied to EUV lithography. In this paper, we report on new developments which extend ILT method to EUV lithography and we characterize the benefits seen vs. traditional EUV OPC/RET methods.
EUV lithography is viewed as a highly desirable technology for 5nm and 7nm node patterning cost reduction and process simplicity. However, for the 5nm and 7nm nodes EUV not only needs to function in a low-K1 resolution environment but has several new and complex patterning issues which will need accurate compensation by mask synthesis tools and flows. The main new issues are: long-range flare variation across the chip, feature dependent focus offsets due to high mask topography, asymmetry inducing shadowing effects which vary across the lens slit, significantly higher lens aberrations, illumination source changes (across the lens and with time) and new resist exposure mechanisms. These solutions must be successfully deployed at low K1 values and must be integrated together to create OPC/RET flows which have high resolution, high accuracy, and are fast to deploy. Therefore, the combined requirements of low-K1 resolution, full reticle correction accuracy and process window can be even more challenging than in current optical lithography mask synthesis flows.
Advanced computational methods such as ILT and model-based SRAF optimization are well known to have considerable benefits in process window and resolution for low-K1 193 lithography. However, these methods have not been well studied to understand their benefits for lower-K1 EUV lithography where fabs must push EUV resolution, 2D accuracy and process window to their limits. In this paper, we investigate where inverse lithography methods can improve EUV patterning weaknesses vs. traditional OPC/RET. We first show how ILT can be used to guide a better understanding of optimal solutions for EUV mask synthesis. We then provide detailed comparisons of ILT and traditional methods on a wide range of mask synthesis applications.
An enhancement to compact modeling capability to include photoresist (PR) loss at different heights is
developed and discussed. A hypsometric map representing 3-D resist profile was built by applying a first
principle approximation to estimate the "energy loss" from the resist top to any other plane of interest as a
proportional corresponding change in model threshold, which is analogous to a change in exposure dose. The
result is compared and validated with 3D rigorous modeling as well as SEM images. Without increase in
computation time, this compact model can construct 3D resist profiles capturing resist profile degradation at
any vertical plane. Sidewall angle and standing wave information can also be granted from the vertical profile
reconstruction. Since this method does not change any form of compact modeling, it can be integrated to
validation and correction without any additional work.
This paper presents a new etch-aware after development inspection (ADI) model with an inverse etch bias filter. We
model the etch bias as a function of pattern geometry parameters, and we introduce it to the ADI model by means of an
inverse bias matrix that works in conjunction with an ADI specification related matrix. The inverse bias filter tunes the
ADI model to be highly correlated to the etch effects and provides simplified and designable inputs to the after etch
inspection (AEI) model and hence improves its performance over the staged modeling flow. In addition, the inverse bias
filter creates a model based rule table for design retargeting. Some of the etch effects are corrected by the inverse bias
filter as the lithography model is calibrated, thus speeding up and simplifying the etch AEI model, while maintaining
lithography ADI model with a good accuracy.
The mechanism of chemically amplified resist plays a critical role in the modeling of the latent image. To achieve a
practical model which can fit into the time frame of OPC, some simplifications and assumptions have to be made. We
introduced regression kernels that take into account best exposure focus difference between isotropic pitch, dense, and
line end features for the evaluation of image intensity. It compares the image intensity (signal) over small changes
above and/or below the regressed "nominal" image position, which in principle corresponds to evaluating the intensity
signal at various depths of a fixed resist profile thus can also be regressed for optimization during model development.
Our calibration has shown that the model brought a great improvement in prediction for difficult structures such as dense
features at or near the optical resolution limit and 2-dimensional features, which are the limiter of the overall model
fitting accuracy for 45nm node and below. By replacing other existing techniques, total number of output kernels used
for OPC operation is actually reduced with improvement of model accuracy. This model is proven to be a very effective
yet accurate addition to the current OPC technology.
Optical Proximity Correction (OPC) has become an integral and critical part of process development for advanced
technologies with challenging k1 requirements. OPC solutions in turn require stable, predictive models to be built that
can project the behavior of all structures. These structures must comprehend all geometries that can occur in the layout
in order to define the optimal corrections by feature, and thus enable a manufacturing process with acceptable margin.
The model is built upon two main component blocks. First, is knowledge of the process conditions which includes the
optical parameters (e.g. illumination source, wavelength, lens characteristics, etc) as well as mask definition, resist
parameters and process film stack information. Second, is the empirical critical dimension (CD) data collected using
this process on specific test features the results of which are used to fit and validate the model and to project resist
contours for all allowable feature layouts. The quality of the model therefore is highly dependent on the integrity of the
process data collected for this purpose. Since the test pattern suite generally extends to below the resolution limit that
the process can support with adequate latitude, the CD measurements collected can often be quite noisy with marginal
signal-to-noise ratios. In order for the model to be reliable and a best representation of the process behavior, it is
necessary to scrutinize empirical data to ensure that it is not dominated by measurement noise or flyer/outlier points.
The primary approach for generating a clean, smooth and dependable empirical data set should be a replicated
measurement sampling that can help to statistically reduce measurement noise by averaging. However, it can often be
impractical to collect the amount of data needed to ensure a clean data set by this method. An alternate approach is
studied in this paper to further smooth the measured data by means of curve fitting to identify remaining questionable
measurement points for engineering scrutiny since they may run the risk of incorrectly skewing the model. In addition
to purely statistical data curve fitting, another concept also merits investigation, that of using first principle, simulation-based
characteristic coherence curves to fit the measured data.
In modern photolithography as the feature sizes reduce, the simulation of manufacturing process calls on more and
more accurate grasp of various effects in the process. While the optical simulation is calculated precisely by both firstprinciple
simulators and optical proximity correction (OPC) model simulator, an accurate and computational inexpensive
resist model has yet to be developed. After the exposure, resist parameters change the resist part of the proximity
effects by either moving the "optical image" or responding differently to varying image qualities. By inspecting the
wafer data, one can only see the results after development, which is the mixture of optical and resist effects. To isolate
the effect contributed by resist, it is necessary to separate the optical component and resist component. In this paper, a
novel method is proposed to determine the resist bias from the iso-focal structure, the critical dimension (CD) of which
was measured under different defocus conditions. The results extracted from experiments indicate that a constant CD
bias can catch most of resist effect at the first order of approximation.