There is growing consensus that 350 nm design rules will be accomplished using i-line lithography. Recent developments in i-line lithography have pushed NA and field size to acceptable levels for 64 MB DRAM manufacturing. Simpler PSM technologies may be used to augment performance in first generation 64 MB DRAM manufacturing. Depending on the topography requirements, it may be necessary to have more process latitude at critical line/space layers. I-line lithography, with conventional binary intensity masks (BIM) should provide adequate process latitude at 400 nm design rules. Incremental improvements in process latitude at feature sizes around this design rule can be obtained using attenuated phase PSM technology. This paper presents data on the implementation of BIM and various PSM technologies in conjunction with a variable NA, variable (sigma) i-line stepper. Optimization of NA and (sigma) have been performed using the various mask technologies to maximize process latitude at features sizes from 450 nm down to below 300 nm. Ultimately, a path is provided to achieve adequate lithographic performance for both first and second generation 64 MB DRAM manufacturing.
I-line lithography, together with single-layer resist processes, practically, have been limited to 0.45 micrometers design rules in the semiconductor industry. For design rules of 0.4 micrometers and below, several contrast enhanced methods have been proposed for i-line lithography, mainly phase shift masks, modified illumination methods, and surface imaging techniques, etc. This paper describes the sub-half micron process performance of 0.48 NA and 0.54 i-line steppers on various topography wafers which are suitable for 0.35 - 0.40 micrometers and 0.40 - 0.45 micrometers design rules. The latest high performance i-line resist and high contrast developing scheme have been chosen for this study. The process windows for the sub-half micron features on various topography wafers are reported. The feasibility to use these processes for the production with lower K1 is also addressed.
Many lithographic approaches to achieving 0.35 micron IC design rules have been proposed. Several years ago, the primary candidate was x-ray lithography. Today it is generally acknowledged that an optical approach will be used for such design rules. Both deep UV and i-line stepper technologies have progressed with capability to achieve 0.35pm design rules. High NA, wide-field lenses now exist for both deep UV and i-line , With the renewed interest in phase shift technology, i-line capability at 0.35pm design rules is comparable to deep UV technology.
The development of a stepper architecture that allows both wide-field i-line and deep UV lenses to be accommodated in the same body and using thru-the-lens, direct-reticle-referenced alignment method  is reported. Common improvements in the areas of stage, die-by-die leveling and environmental control allow exceptional overlay performance to be achieved for both i-line and deep UV. The use of common architecture and the same alignment method facilitates the optimum mix and match combination of i-line and deep UV at
0. 35?m design rules
Experimental investigation of stepper performance is reported in comparison to criteria established for design rules at 0.35pm. Overlay is evaluated on substrates typical of CMOS IC manufacturing. Lithographic performance is investigated using conventional techniques as well as more advanced techniques including phase shift reticles.
Results indicate that overlay performance on tested substrates meets the requirements for 0.35?m design rules. Lithographic results indicate that 0.35pm lines/spaces are achievable using both conventional i-line and deep UV techniques, however, the implementation of phase shift reticles enhances the process latitudes for i-line at 0.35?m.
High packing density integrated circuits such as 4 MB DRAM require many interconnect layers. The resulting topography can be very challenging at each layer, particularly for patterning contacts. This paper provides practical techniques for imaging submicron contact holes on topographical substrates. Patterning is done using a 0.48 NA i-line stepper, and methods for achieving 0.5 micrometers contact holes and other features on topographical substrates are described. Results for process latitudes, depth of focus, and feature size dependencies are reported.
i-line wafer steppers are evolving as established production tools, and it is evident that they will be used to realize features in the sub-half-micron region. Consequently, i-line steppers can be expected to be the equipment of choice for volume production of 16 MBit DRAMs and possibly the first generation of 64 Mbit devices, before the introduction of DUV lithography. However, for this sub-half-micron resolution, lenses with higher apertures and large field sizes will be required. In this paper a new family of wafer steppers is introduced, with a new mechanical frame design and modular architecture which can accommodate a family of large field i-line and deep UV lenses. Results from the first lens type with NAequals0.54 and a field diameter of 25.5 mm are described. To overcome the anticipated depth of focus problems on production wafers, a field-by-field leveling system is introduced, ensuring optimum focus over the whole image field. A challenging problem of wafer steppers using this option is the alignment accuracy during stepping of stage and active leveling of the wafer chuck. The stepper concept introduced here is able to realize the field-by-field leveling without the need for the throughput consuming field-by-field alignment. For that purpose a wafer stage with a new metrology system and improved accuracy has been designed, resulting in an overlay accuracy better than 85 nm in the global alignment mode. Simultaneously a throughput of more than 80 150 mm wafers per hour is realized. Along with the new lens and metrology concept, the stepper contains local environmental control systems performing better than class 1, to ensure clean handling of 8-inch wafers without the need for space consuming environmental enclosures. This paper reports practical results from the new stepper, including resist features below 0.4 micrometers , overlay measurements, particle control, as well as a general description of the new stepper architecture.
I-line stepper technology is described which features a new generation high NA lens and an improved implementation of a phase grating alignment system. Combining the high NA lens with high contrast resist processing enables O.5um processing to be supported with good process latitude and CD control without adverse effects due to lens heating. Alignment technology compatible with advanced processing is described. Overlay data taken from several steppers shows less than lOOnm capability which is sufficient to support O.5um design rules. Further advancements in Iline processing technology to O.41um are described which allows this technology to be used in developing advanced products.