In this paper, we describe an integrated design space analysis approach consisting of full factorial layout
generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo
simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick
turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable
design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and
cell boundary situations, which are critical for a place and routed block. These interconnects developed using the
integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T
libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.
In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX™, novel Middle-of-Line
(MOL) constructs have been specifically enabled. The Gate Tie-Down (or “continuous RX”) construct allows an optimal
device performance without loss of area. A method for a silicon-based evaluation and optimization of the Gate Tie-Down
construct is presented here. We discuss the main design-process failure modes, their severity and the risk mitigation
options. A full-factorial Design of Experiment used for the construct validation is presented and analyzed. Two critical
failure modes are isolated and discussed. As a final step, the optimized design is validated over a much larger number of
occurrences, showing a robust 4-sigma manufacturing design margin.