Reducing the overlay error between stacked layers is key to enabling higher pattern density and thus moving towards high performance and more cost effective devices. However, as for specific applications like macrochips with photonic interconnects and high-resolution image sensor flat panels with advance polarizers, customers require product field sizes that are larger than the maximum field size available on scanners. Those large fields are obtained by stitching together multiple standard fields. The overlay performances between two adjacent dies are as aggressive as what is usually required between two stacked layers. For this application, the well-established polynomial overlay model is not suitable as the displacement is measured relatively and the metrology sampling in the field is such that some high order nonlinear (K) terms cannot be modeled independently. Furthermore, a perfect grid is needed in mix and match production. The intrafield correction capability of the exposure tool is not the same for each process steps. For example, no intrinsic K13 can be printed for a mix and match process flow that includes an Extreme Ultra-Violet (EUV) litho step. In addition, some KrF scanners with fewer lens manipulators cannot correct for K9. Measuring the stitching and correcting it at the first layer will prevent printing K terms that are not correctable later in the process. In this paper, the need to characterize and control single-layer overlay among different pattern placement mechanisms intrinsic to the scanner was studied: optical aberrations, field-to-field position, mask placement and registration. An ASML set-up BP-XY-V3 reticle was used to generate a large experimental dataset to validate stitching models supported by Overlay Optimizer (OVO). Overlay measurements were done Resist-in-Resist using new YieldStar (YS) interlaced stitching Diffraction Based Overlay (μDBO) targets that were designed and validated. This paper will present on product metrology results of a scatterometry-based platform showing production results with focus not only on precision and on accuracy, but also assessing target performance and target-to-target delta without process influence. A high order stitching model was developed and verified on a Multi-Product Reticle for a large device application. Trench width control at the field intersection was studied then optimized with proximity correction to ensure a perfect field-to-field junction.
With continuous shrink in feature dimensions, overlay tolerance for fabrication of transistors is getting more stringent. Achieving good overlay is extremely critical in getting good yield in HVM environment. It is widely understood that good alignment during exposure is critical for better on product overlay [1]. Conventional methods to choose alignment marks on ASML scanners are based on comparing alignment key performance indicators (KPIs) including signal quality, grid repeatability, etc. It is possible that even with good alignment KPIs, OPO is still impacted. In this paper, we propose aspects that need to be monitored to choose proper alignment marks. LIS (Litho In-Sight) alignment, Ideal overlay/APC parameter signatures are used to determine and validate wafer alignment. LIS alignment ‘Target and Profile selection’ analysis enables us to determine best alignment strategy between multiple strategies/marks based on overlay measurements. Analysis includes examining wafer to wafer OPO variation which is key indicator for alignment robustness. Varying overlay parameters within lot would indicate either large process instability or alignment mark signal instability. It is possible that alignment marks depending on their segmentation can be very differently impacted with the process. Ideal overlay/APC signature stability indicates healthy process and wafer alignment. Having similar APC signatures at corresponding layers would mean that there is no major process or alignment issue.
Wafers at FBEOL layers traditionally have higher stress and larger alignment signal variability. ASML’s ATHENA sensor based scanners, commonly used to expose FBEOL layers, have large spot size (~700um). Hence ATHENA captures the signal from larger area compared to the alignment marks which are typically ~40um wide. This results in higher noise in the alignment signal and if the surrounding areas contain periodic product structures, they interfere with the alignment signal causing either alignment rejects or in some cases- misalignment. SMASH alignment sensors with smaller spot size (~40um) and two additional probe lasers have been used to improve alignment quality and hence reduce mark/wafer rejects. However, due to the process variability, alignment issues still persist. For example, the aluminum grain size, alignment mark trench deposition uniformity, alignment mark asymmetry and variation in stack thicknesses all contribute to the alignment signal variability even within a single wafer. Here, a solution using SMASH sensor that involves designing new alignment marks to ensure conformal coating is proposed. Also new techniques and controls during coarse wafer alignment (COWA) and fine wafer alignment (FIWA) including extra controls over wafer shape parameters, longer scan lengths on alignment marks and weighted light source between Far Infra-Red laser (FIR) and Near Infra-Red (NIR) for alignment are presented. All the above mentioned techniques, when implemented, have reduced the wafer alignment reject rate from around 25% to less than 0.1%. Future work includes mark validation based on the signal response from the various laser colors. Finally, process monitoring using alignment parameters is explored.
To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.
Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC
processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of
overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and
unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and
linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment
cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes.
Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic
errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid
distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment
data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are
calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated.
How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and
matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This
evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product
specific corrections per exposure and 10 term APC process control.
Negative tone development (NTD) processes have been widely explored as a way to enhance the printability of
dark field features such as contact holes and trenches. A key consequence of implementing NTD processes and
subsequent tone reversal of dark field reticles is the significantly higher transmission of bright field masks and thus
higher light intensity in the projection optics. This large increase in mask transmission coupled with the higher
throughput requirements of multiple patterning and the use of freeform illumination created by source mask
optimization creates a significant amount of lens heating induced aberrations that must be characterized and
mitigated. In this paper, we examine the lens heating induced aberrations for high transmission reticles common
to NTD using both simulations and experiments on a 193 immersion lithography tool. We observe a substantial
amount of aberrations as described by even and odd order Zernike drifts during the course of a wafer exposure lot.
These Zernike drifts per lot are demonstrated to have the following lithographic effects: critical dimension shifts,
pitch dependent best focus shifts and image placement errors between coarse and fine patterned features. Lastly,
mitigation strategies are demonstrated using various controllers and lens manipulators, including FlexWave with
full Zernike control up to Z64, to substantially reduce the lens heating effects observed on-wafer.
Continued lithographic pattern density scaling depends on aggressive overlay error reduction.1,2 Double patterning
processes planned for the 22nm node require overlay tolerances below 5 nm; at which point even sub-nanometer
contributions must be considered. In this paper we highlight the need to characterize and control the single-layer
matching among the three pattern placement mechanisms intrinsic to step&scan exposure - optical imaging, mask-to-
wafer scanning, and field-to-field stepping. Without stable and near-perfect pattern placement on each layer,
nanometer-scale layer-to-layer overlay tolerance is not likely to be achieved. Our approach to understanding onwafer
pattern placement is based on the well-known technique of stitched field overlay. We analyze dense
sampling around the field perimeter to partition the systematic contributors to pattern placement error on
representative dry and immersion exposure tools.
Many factors are driving a significant tightening of the overlay budget for advanced technology nodes, e.g.
6nm [mean + 3σ] for 22nm node. Exposure tools will be challenged to support this goal, even with tool
dedication. However, tool dedication has adverse impact on cycle time reduction, line productivity and cost
issues. There is a strong desire to have tool to tool (and chuck to chuck) matching performance, which supports
the tight overlay budgets without tool dedication. In this paper we report improvements in overlay metrology
test methods and analysis methods which support the needed exposure tool overlay capability.
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion
lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer,
intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library
development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay
performance with immersion lithography is also presented.
In this paper we performed an analysis of various data collection preformed on C045 production lots in order to
assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to
show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners
combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers.
After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process
windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible,
in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to
achieve a better global CD uniformity.
KEYWORDS: Modulation, Critical dimension metrology, Electron beam direct write lithography, Point spread functions, Electron beam lithography, Cadmium sulfide, Electron beams, Optical lithography, Manufacturing, Backscatter
After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by backscattering electrons and others phenomenon. In this work, the limitations of the dose modulation method are investigated through the change of dose number steps and the use of a more accurate point spread function. To continue reducing feature sizes, a method to provide a complementary correction to the dose modulation solution is proposed. This rule-based electron beam proximity correction, or REBPC, provides good results down to 40 nm.
Proc. SPIE. 6533, 23rd European Mask and Lithography Conference
KEYWORDS: Electron beam lithography, Point spread functions, Electron beams, Scattering, Laser scattering, Monte Carlo methods, Optical simulations, Convolution, Electron beam direct write lithography, Photoresist processing
Electron Beam Direct Write (EBDW) is involved today in advanced devices
manufacturing and technology node development. As a consequence, EBDW is supporting an
increasing number of technologies and several layers per technology. In this context, an
EBDW simulator can strongly help this development study and reduce process development
cycle time. Today, available EBDW simulators are based on the use of a Point Spread
Function (PSF) to describe the energy absorbed into the resist during exposure and resist
models. Beside a constant improvement of these models limitations are observed in simulation
of sub-45nm nodes. In this paper, several simulation methods are investigated with the
purpose to build a simulation method relevant for sub-45nm nodes. The limitations of classical
EBDW simulation based on a full process flow simulation are evaluated for line width below
100nm. Then, a reduced process flow simulation limited to the exposure step is investigated
with the use of both a simulated PSF and an empirical PSF. We will see that the approach to
use an empirical PSF with the reduced process flow simulation has good predicting
capabilities in simulating structures down to 40nm.
With the strong increase of mask complexity and associated price for each new technology node, mask less lithography represents more and more an interesting and complementary alternative for ASIC manufacturing especially in the fields of low volume and leading eadge technology applications. In the semiconductor business where prices and cycle time are constantly pressured, the capability and flexibility of the electron beam direct write offer an effective real cost and cycle time opportunity thanks to its high-resolution capability but also to its ability to print, modify or correct design everywhere in a circuit. This paper highlights application examples where the advantages of this lithography solution are demonstrated for advanced research and development application with the patterning of 45 nm SRAM and for the fast validation of architecture designs. This work confirms that mask less lithography can be transparently placed into production environment, in association with the "golden" optical lithography reference.
Proc. SPIE. 5753, Advances in Resist Technology and Processing XXII
KEYWORDS: Semiconductors, Electron beam lithography, Electron beams, Etching, Coating, Manufacturing, Line width roughness, Electron beam direct write lithography, Photoresist processing, Semiconducting wafers
Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments. Patterning for sub-45nm node technology requires the development of high performance processes. Different alternatives for the improvement of EBDW lithography are investigated in this paper for the ASIC manufacturing on 300mm wafer size. Among them, process development has been tuned for clear field equivalent level to improve both line width roughness by monitoring post applied bake conditions, and both process window by specific design correction. Concerning dark field level, process resolution has been improved by a shrinkage technique.
This paper presents a systematic theoretical and simulation study on how scattering bar could impact lithographic performance in the presence of lens aberrations. In particular, the effects of bar size, bar placement and pitch at conventional and annular illuminations are investigated. For the study, a simple 1-D two-bar structure is used. The effects of odd and even aberration terms are studied assuming the presence of either primary coma or primary astigmatism only. Simulations using a set of 37 Zernike coefficients from a state-of-the-art DUV step and scan are also carried out. Pattern asymmetry of the two-bar pattern is used to quantify the effects of odd aberration terms; the root-mean-square value of CD difference through focus of two orthogonal lines is used to quantify the effects of even aberration terms. Results show that scattering bar has a significant impact on the effects of lens aberrations. The magnitude and polarity of this influence depends on the bar size, bar placement, pitch and illumination conditions. Pattern asymmetry under annular illumination is particular sensitive to bar size and bar placement; CD difference through focus under conventional illumination at a range of pitch values decrease significantly with proper bar placement. The trends observed are similar even when a full set of Zernike coefficients are used. A thorough and more complete understanding of how scattering bar impact lens aberration effect for different mask structures and at different illumination conditions is thus needed for low-k1 imaging.
The aim of this paper is to investigate the intrafield flare distribution and its link with the intrafield CD variation for various ASML lithographic tools. Flare is measured as the required dose to clear a 100micrometers -large positive resist pattern and comparing it with dose-to-clear Eo. The reticle layout used is compared of a repetitive cell which allows for 77 measurements within a single 22 X 22 mm2 field. Experimental results show that in the field of a stepper, flare decreases almost linearly form center to edge. In the field of a scanner, the flare distribution result from the distribution inside the illumination slit which is ellipsoidal. Comparing the intrafield flare distribution to the intrafield CD uniformity , it appears that flare is responsible for a part of the across field CD variation. We will see in this paper how it is possible, using a method based on statistical considerations, to decorrelate both the contributions of mask CD errors and flare variation to the intrafield CD dispersion for dense lines and 1/3 for isolated lines. The intrafield flare variation is also found to contribute a lot to the signature of the CD uniformity and to the 3 sigma dispersion.
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