We fabricated large-area stacked complementary plasmonic crystals (SC PlCs) by employing ultraviolet nanoimprint lithography. The SC PlCs were made on silicon-on-insulator substrates consisting of three layers: the top layer contacting air was a perforated Au film, the bottom layer contacting the buried oxide layer included an Au disk array corresponding to the holes in the top layer, and the middle layer was a Si photonic crystal slab. The SC PlCs have prominent resonances in optical wavelengths. It is shown that the fabricated PlCs were precise in structure and uniform in their optical properties. We examined the photoluminescence (PL) enhancement of monolayer dye molecules on the SC PlC substrates in the visible range and found large PL enhancements of up to a 100-fold in comparison with dye molecules on nonprocessed Si wafers.
We fabricated large-area stacked complementary plasmonic crystals (SC PlCs) by employing ultra-violet (UV) nanoimprint lithography (NIL). The SC PlCs was made on silicon on insulator (SOI) substrates, consisting of three layers: the top layer contacting air was perforated Au film, the bottom layer contacting buried oxide (BOX) layer included Au disk array corresponding to the holes in the top layer, and the middle layer was Si photonic crystal slab. The SC PlCs have prominent resonances in the optical wavelengths. It is shown that the fabricated PlCs were precisely made in structure and well uniform in the optical properties. We have examined photoluminescence (PL) enhancement of dye molecules on the SC PlC substrates in the visible range and found large enhancement up to 100-fold in comparison with the dye molecules on non-processed Si wafers.
The shrink of device node to raise the integration is important for the raising of cost performance on memory device.
Targeting the feature critical dimension (CD) and defect control to achieve a large process margin and high product yield
become an essential management point under the node shrink, thus sufficient works have been progressed on the product
level. In the immersion lithography, the performance of CD and defect control range is intensively improved because of
high equipment performances. However, proximity effect causes the CD variation and unknown hotspots because of
environmental variation. In this work, control of the CD errors and hotspots will be discussed by using a verification
system with an image verifier algorithm between design layout and wafer images. We used NGR2100TM as a verification
system. The verification works for the CD distributions and hotspot detection are implemented on sub 50 nm node
memory device. In the experiment, improved CD distributions were examined based on retarget correction for CD errors
and the controllability of hotspots are explained from the examined methodology.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.