The ability to convert high resolution images from a Scanning Electron Microscope (SEM) of a printed
lithographic pattern to a GDS image file which can be input into modeling software (such as litho-simulation,
etc.) for rigorous analysis is a powerful tool. Its use can be expanded through the simplication of the SEM2GDS
conversion procedure by automation of the tasks. In this paper, we describe our SEM2GDS and SCAN
INTERFACE UNIT, which automates both SEM image collection and SEM2GDS conversion.
The concept of using Scanning Electron Microscopy and Die-to-Database techniques to rigorously inspect advanced lithography products such as X-ray Lithography, Imprint, and Stencil masks as well as other Next Generation Lithography (NGL) is compelling. Current optical capabilities reach down to 0.2μm and do so by interpolating pixilated optical data. Applications at 4x magnifications, such as Chrome on Glass or Phase Shift Photomasks mesh with this resolution of inspection and have been able to migrate down the lithography nodes hand in hand. As the demands for resolution progress, optical lithography has been increasing the requirements upon inspection systems presently available through the addition of assist features and serifs, which are difficult to directly verify. These assist features are effectively approaching 1x dimensions. A printed feature that is slightly out-of-tolerance for CD, shape, or position relative to other structures, may still yield acceptable performance. This added resolution challenge of working closer to a 1x Magnification with ever decreasing structure sizes is easily achieved with Scanning Electron Microscope technology. The Die-to-Database inspection technique utilizes the CAD image, which defines the designer's original intended structure, as the reference image.
In this paper, we will introduce a revolutionary approach for utilizing the full potential of Scanning Electron Microscope images for inspection purposes. The technique incorporates an aggressive but reliable interpretation of the image data to recreate GDS data files which can then be validated against the desired GDS data for hard defects, abbreviated / missing features, and even shifts or placement errors.
Proximity lithography places a thin membrane mask into close proximity (5-100 micron) to a wafer for exposure to radiation and pattern placement. Efficient production practices require that the wafer be positioned relative to the mask as quickly as possible. The positioning maneuvers involve both a lateral motion and a closing of the mask-to-wafer gap. Gap closing requires forcing the exposure chamber gas (usually air or helium, possibly at a mild vacuum) between the mask and wafer out through the edges of the gap in a squeeze film process that can substantially deflect and damage the membrane mask. Moving laterally, i.e. stepping, would be more efficient if it were performed at the close proximity gap. The buildup of hydrodynamic pressures while stepping at gap can deform and possibly damage the mask. This paper discusses methods to model, measure and control aeroelastic effects due to gap closing and lateral stepping at gap. The analysis considers an aeroelastic model based on coupling Reynolds' hydrodynamic lubrication theory with membrane mechanics. A principal result of the analysis is the prediction that it is possible to step at gap and produce minimal aeroelastic out-of-plane deflections, if the wedge angle is zero, and both the membrane and mask have a flat profile. The aeroelastic models are confirmed with experiments that measure out-of-plane stepping of a membrane versus wedge angle, gap and speed. Non-flat mask profiles, such as buttes and mesas raise additional aeroelastic issues are also examined.
Collimated laser-Plasma Lithography (CPL) offers potential to match Next Generation Lithography (NGL) needs, ending a pursuit of ever-larger lens NA and ever-smaller k1 process resolution factor. Powered by a laser-produced plasma (LPP) source at 1nm, it capitalizes on mature development of x-ray lithography, which is the only NGL that has produced working chips. JMAR is upgrading its CPL system to increase overall throughput (system power) and is focusing on solving a known industry problem for which CPL presents an advantage: printing sub-90nm contacts in memory chips.
The paper will discuss CPL system characteristics and performance. Supporting information on the upgrades to the laser and x-ray generator will be included. Specific resists and mask techniques and the roadmap leading to multi-generational support capability down to the 45nm node will be described.
A new fabrication process flow is being developed for X-ray lithography masks to simplify the wafer bonding procedure while allowing for the use of a standard, non-distortive mount in the e-beam tool. A conventional flow includes a support ring that is anodically-bonded to the mask wafer prior to writing the pattern in the e-beam tool. The new flow includes a support ring that is bonded to the mask wafer at a “single point” after the pattern is written. Because mask membrane distortions due to fabrication, pattern transfer, and mounting give rise to image placement errors on the device wafer, this research focused on the impact the new process flow has on mask membrane distortions in comparison to those that result from a conventional process flow. The resulting simulations showed that distortions that lead to image placement errors decrease when employing the new fabrication process. The results also illustrate that mechanical modeling provides an invaluable tool for quantifying image placement errors, and, ultimately, optimizing the system parameters to successfully meet the stringent error budgets at the 45-nm node (and below).
JMAR develops Laser-Produced Plasma (LPP) sources for lithography applications, and has specifically developed Collimated laser-Plasma Lithography (CPL) as a 1 nm collimated point source and stepper system to address sub-100nm lithography needs. We describe the CPL source development, show demonstrated sub-100nm printing capability, and describe status of a beta lithography tool. The system will be power-scaled to address silicon device contacts and vias at 90nm and below. This development has much in common with LPP Extreme UltraViolet Lithography (EUVL) sources; an EUV source concept is presented to address the high power requirements of that Next Generation Lithography (NGL).
In the world of micro- Lithography, several options exist for obtaining features below the 100nm level. Options include a variety of methods which range from additional process steps in etch, multilayer resist systems, or expensive throughput limited direct write E-beam systems. Each comes with a handful of trade offs in uniformity, repeatability and cost. Collimated (LASER) Plasma Lithography (CPL), on the other hand offers a full field exposure with minimal process intervention to obtain resolution below the 100nm barrier. CPL, uses a membrane 1x proximity mask and a collimated light source with energy peaking at 11 A°. By using a mask, an entire 22mm x 22mm field (30mm x 30mm with the next generation) can be exposed at once regardless of chip density, removing any throughput concerns as well as placement, stitching and typical E-beam machine flaw defects. Collimation, provides a predictable flux of energy to ensure minimal global divergence and energy level variation. Energy at 11 A°, allows for a high level of uniformity and penetration within the resist, without introducing resolution compromising scattering or standing wave effects.
This Paper will demonstrate the capabilities of CPL as well as the advantages over traditional lithography in obtaining features below 100nm. We will also depict process techniques which take full advantage of improvements in CAR, and experiments which suggest reduction possibilities through variables in mask fabrication.