We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics
process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a
hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter
and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used
to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a
design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher
speeds and channel counts.
We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial
CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs
encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated
circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule
checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of
integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission
speed and report on its performance.
Three oscillators are presented for operation in the 23-25 GHz range where consideration is given to noise, frequency, and power effects of different tank sizes and topologies. The circuits in question employ inductor based tanks with negative resistance provided through an emitter degenerated cross-coupled pair, and use emitter degeneration and inductive peaking to provide bandwidth extension within the single stage output buffers. These circuits are implemented in a 0.18 μm SiGe BiCMOS technology with a 54 GHz ft, and use single device stacks to achieve low voltage operation with VDD as low as 900 mV, while consuming as little as 2.25 mW of power.
An integrated 18 GHz double-balanced direct down-conversion mixer and emitter degenerated quadrature VCO is designed and fabricated in IBM 47 GHz ft SiGe BiCMOS process. A novel headroom optimization scheme is proposed to optimize mixer conversion gain and linearity. The mixer uses an LC tank to reduce voltage supply. With a 3.3 V supply voltage the mixer core consumes 16.5mW and the output buffer matched to 50 Ω consumes 33mW. Measurements indicate a conversion gain of 4.5 dB, a double-side band noise figure of 7.1dB, an IIP3 of -1dBm, and 1dB compression point at -12.2dBm output power. The mixer has the best figure-of-merit compared to recently published mixers operating at similar frequencies in a Si-based process. The voltage controlled oscillator uses an emitter degenerated LC oscillator core with both SiGe HBT and CMOS buffers to achieve oscillation providing direct downconversion for the aforementioned mixer. The oscillator has two anti-phase coupled cores to lower the phase noise through frequency locking, the unused output ports terminated with 50 Ω. The two circuits (several variants of each) are integrated monolithically, with an oscillator breakout with a phase noise performance of -99 dBc/Hz (at 1 MHz separation) with 1 GHz tuning range while pulling 19 mA from a 2.5 V rail. The paper will include all the necessary design equations used to optimize both circuits along with comparisons with other published results.