Traditionally, optical proximity correction (OPC) on cell array patterns in memory layout uses simple bias rules to correct hierarchically-placed features, but requires intensive, rigorous lithographic simulations to maximize the wafer process latitude. This process requires time-consuming procedures to be performed on the full chip (excluding the cell arrays) to handle unique cell features and layout placements before (and even sometimes after) OPC. The time required limits productivity for both mask tapeouts and the wafer process development. In this paper, a new cell array OPC flow is introduced that reduces turnaround-time for mask tapeouts from days to hours, while maintaining acceptable OPC quality and the perfect geometric consistency on the OPC output that is critical for memory manufacturing. The flow comprises an effective sub-resolution assist features (SRAFs) insertion and OPC for both the cell array and the peripheral pattern areas. Both simulation and experimental results from actual wafer verification are discussed.
State of the art Extreme Ultra Violet Lithography (EUVL) gives high hope for further shrinkage of
semiconductor devices, but currently, EUVL is not ready for 2xnm node manufacturing and ArF immersion
must extend its capability in manufacturing 2xnm devices. Extending the limit of ArF requires varieties of
Resolution Enhancement Techniques (RET) such as inverse lithography (ILT) , double patterning (DPT),
spacer patterning and so on. One of the brightest candidate for extension of ArF for contact layer is negative
tone development (NTD), since this process utilizes the high contrast of the inverse tone of the mask for
patterning. NTD usually results in high process margin compared to conventional positive tone development
Therefore, in this paper we will study application of NTD from optical proximity correction (OPC)
and simulation perspective. We will first discuss difference of NTD from PTD. We will also discuss on how
to optimize NTD process in simulation perspective, from source optimization to simulation calibration. We
will also discuss what to look out for when converting PTD process to NTD process, including OPC models
to design rule modification. Finally, we will demonstrate the superiority of NTD process through modeling
and simulation results with considering these factors mentioned above.
As the DRAM node shrinks down to its natural limit, photo lithography is encountering many difficulties.
3Xnm DRAM node seems to be the limit for ArF Immersion. Until the arrival of EUV, double patterning (DPT) or
spacer double patterning (SPT) seems like the next solution. But the problem with DPT or SPT is that both increases
process step their by increasing the final costs of the device. So limiting the use of DPT or SPT is very important for
device fabrication. For 3Xnm DRAM, storage node is one of the candidates to eliminate DPT or SPT process. But this
method may cost lower process margin and degradation of pattern image. So, solution to these problems is very crucial.
In this study, we will realize storage node (SN) pattern for 3Xnm DRAM node with improved process margin. First we
will discuss selection of illumination for optimal condition second, correction of the mask will be introduced. We will
also talk about the usage of various RET such as model based assist feature. Value such as DOF, EL and CDU (critical
dimension uniformity) will be evaluated and analyzed.
In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared
and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at
IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to
simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured
and compared with simulation result to match the predictability of the simulation tool.
Shadowing test comparison of wafer to simulation showed that simulation with resist model
showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within
2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error
RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher
accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist
model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool
showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and
shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using
EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.
One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography.
In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirk's disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.
Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact holes pattern. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn't meet the overall expectations.
In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact holes pattern, which utilizes two thousands of real contact holes pattern to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.
As the semiconductor feature size continues to shrink, electrical resistance issue is becoming one of the
industry's dreaded problems. In order to overcome such problem, many of the top semiconductor manufacturers have
turned there interest to copper process. Widely known, copper process is the trench first damascene process which
utilize dark tone mask instead of widely used clear tone mask. Due to unfamiliarity and under development of dark tone
mask technology compared to clear tone mask, many have reported patterning defect issues using dark tone mask.
Therefore, necessity of DFM for design that meets both dark and clear tone is very large in development of copper
process based device.
In this study, we will propose a process friendly Design For Manufacturing (DFM) rule for dual tone mask.
Proposed method guides the layout rule to give same performance from both dark tone and clear tone mask from same
design layout. Our proposed method will be analyzed on photolithography process margin factors such as Depth Of
Focus (DOF) and Exposure Latitude (EL) on sub 50nm Flash memory interconnection layer.
As the semiconductor industry continues progressing toward increasingly complex and
unforgiving processes of device shrinkage and shorter duration of device development, many
industry participants from photo-lithography are taking interest in material and structure of the
photolithography mask. Due to shorter wavelength of the source laser and device technology
ranging around the order of magnitude for the source laser wavelength (ArF), the difference in mask
material and structure shows greater performance difference then larger technology node. Especially
around 50nm and beyond, many industry followers are reporting better performance from different
types of mask then previously used.
In this study, we will analyze the effect of the photo lithography mask material for sub
50nm device, in development perspective. Two major types of mask will be evaluated on the scale
of device development. Effects such as Mask Error Effect Factor (MEEF), Depth of Focus (DOF),
Exposure Latitude (EL) and Critical Dimension Uniformity (CDU) will be analyzed for both binary
and attenuated phase shifted mask under different process condition. Also, we will evaluate the
comparison result for application on development of sub 45nm device.
Over the last couple of years, Design For Manufacturability (DFM) has progressed from concept to practice.
What we thought then is actually applied to the design step to meet the high demand placed upon very high tech devices
we make today. One of the DFM procedures that benefit the lithography process margin is generation of dummy
patterns. Dummy pattern generated at design step enables stable yet high lithography process margin for many of the
high technology device. But actual generation of the dummy pattern is very complex and risky for many of the layer
used for memory devices. Dummy generation for simple pattern layers such as Poly or Isolation layer is not so difficult
since pattern composed for these layers are usually 1 dimensional or very simple 2 dimensional patterns. But for
interconnection layers that compose of complex 2 dimensional patterns, dummy pattern generation is very risky and
requires lots of time and effort to safely place the dummy patterns.
In this study, we propose simple self assembled dummy (SAD) generation algorithm to place dummy pattern
for the complex 2 dimensional interconnection layers. This algorithm automatically self assembles dummy pattern
based on the original design layout, therefore insuring the safety and simplicity of the generated dummy to the original
design. Also we will evaluate SAD on interconnection layer using commercial Model Based Verification (MBV) tool to
verify its applicability for both litho process margin and DFM perspective.
The modeling of the resist development is an important tool in the study of lithography. Many papers reported the importance of the develop rate change near the resist surface, but Mack's lumped parameter model ignored the develop rate change near the resist surface and they treated the absorption coefficient as a constant. We included the resist surface effect by changing the absorption coefficient as a function of resist depth and we can predict more realistic resist sidewall angle near the resist surface. We also noticed that the resist sidewall angle can be changed by numerical aperture and partial coherence variation. Higher numerical aperture and smaller partial coherence give not only better resolution at the resist bottom, but also more vertical sidewall angle around the resist surface.
The halftone mask, also called the attenuated phase shifting mask, is assumed to be a preferred candidate among many types of masks since it can be applied to all feature types and it is relatively easy to fabricate. We studied the process latitude of the halftone mask with normal illumination and the combination of the halftone mask with off-axis illumination by computer simulation, the fabrication of the halftone mask, and exposure with an i-line stepper. The greatest improvement of process latitude can be achieved for contact hole pattern when the halftone mask is used. The isolated space and the isolated line pattern show minimal gain by the halftone mask or the off-axis illumination, but the line/space pattern can be made by the off-axis illumination. The process latitude can be enlarged by the proper mask bias and the aspect ratio.