As the semiconductor device dimension continues to shrink, the tolerance of Critical Dimension (CD) variation has been dramatically reduced for whole chip area to ensure the good uniformity of device functionality. Accordingly, the Optical Proximity Correction (OPC) model accuracy has become extremely important for controlling across-chip CD variation. The traditional method relying on CD Scanning Electron Microscope (CD-SEM) measurement data from synthetic patterns, such as dense line/space and isolated line in various pitch biases, for OPC model calibration is no longer sufficient for accurately projecting the complex patterns such as asymmetrical layout environments. Alternatively, the 2D extracted contours from SEM images associated with user-specified cutline algorithm to get the dimensional information of complex patterns have been incorporated for OPC modeling as well as process qualification [1-3]. In this work, the 2D contour extraction methodology was incorporated to extract more comprehensive CD information of complex features for OPC model calibration of 39nm half-pitch process layer. Together with the use of CD-SEM based CD, the model calibration via MASK2D and MASK3D model forms were conducted for accuracy comparison. The OPC model validation results demonstrated the contour-based gauges helps to improve the OPC model projection accuracy by 40~60% for asymmetrical features comparing to the traditional OPC calibration method.
As design pitch shrinks to the resolution limit of up-to-date optical lithography technology, the Critical Dimension (CD) variation tolerance has been dramatically decreased for ensuring the functionality of device. One of critical challenges associates with the narrower CD tolerance for whole chip area is the proximity effect control on asymmetrical layout environments. To fulfill the tight CD control of complex features, the Critical Dimension Scanning Electron Microscope (CD-SEM) based measurement results for qualifying process window and establishing the Optical Proximity Correction (OPC) model become insufficient, thus 2D contour extraction technique [1-5] has been an increasingly important approach for complementing the insufficiencies of traditional CD measurement algorithm. To alleviate the long cycle time and high cost penalties for product verification, manufacturing requirements are better to be well handled at design stage to improve the quality and yield of ICs. In this work, in-house 2D contour extraction platform was established for layout design optimization of 39nm half-pitch Self-Aligned Double Patterning (SADP) process layer. Combining with the adoption of Process Variation Band Index (PVBI), the contour extraction platform enables layout optimization speedup as comparing to traditional methods. The capabilities of identifying and handling lithography hotspots in complex layout environments of 2D contour extraction platform allow process window aware layout optimization to meet the manufacturing requirements.
As patterns shrink to the resolution limits of up-to-date ArF immersion lithography technology, negative tone development (NTD) process has been an increasingly adopted technique to get superior imaging quality through employing bright-field (BF) masks to print the critical dark-field (DF) metal and contact layers. However, from the fundamental materials and process interaction perspectives, several key differences inherently exist between NTD process and the traditional positive tone development (PTD) system, especially the horizontal/vertical resist shrinkage and developer depletion effects, hence the traditional resist parameters developed for the typical PTD process have no longer fit well in NTD process modeling. In order to cope with the inherent differences between PTD and NTD processes accordingly get improvement on NTD modeling accuracy, several NTD models with different combinations of complementary terms were built to account for the NTD-specific resist shrinkage, developer depletion and diffusion, and wafer CD jump induced by sub threshold assistance feature (SRAF) effects. Each new complementary NTD term has its definite aim to deal with the NTD-specific phenomena. In this study, the modeling accuracy is compared among different models for the specific patterning characteristics on various feature types. Multiple complementary NTD terms were finally proposed to address all the NTD-specific behaviors simultaneously and further optimize the NTD modeling accuracy. The new algorithm of multiple complementary NTD term tested on our critical dark-field layers demonstrates consistent model accuracy improvement for both calibration and verification.
OPC (Optical Proximity Correction) has been employed for over decade to address local lithographic printing effects. With the intensive scaling down of the designs as well as the increasing complexity of layout routing, lithographic process is being pushed to its theoretical limit and it has led to continuously shrinking DoF (Depth of Focus). Complex OPC model components are hence included into optical lithography simulation to ensure tolerable CD (Critical Dimension) variation and sustainable DOF of concerned layouts. For example, very complicated segmentation needs to be applied in mask correction, which comes at the cost of long runtime and requires an effective approach to consolidate the adequacy of model components during the flow of correction parameter tuning. In this paper, an approach is demonstrated to improve the accuracy and efficiency of OPC parameter tuning for mask correction. The approach starts with analyzing the target points in post-OPC database to identify those intolerable variations, followed by a pattern similarity grouping for the above intolerable layouts. Then, a concern index is established based on the CD out-of-tolerance ratio, dissection and pattern type for prioritizing the problematic variations. Then the corrective parameters are accordingly optimized to reduce the variation on highly prioritized patterns. During the iteration flow of OPC parameter optimization, the combination of pattern grouping and concern index greatly reduces required optimization iterations for OPC recipe tuning and enhances OPC convergence.
To avoid the dramatically diminishing of lithography process window as the shrink of design rule, the implementation of process-aware optical proximity correction (PWOPC) has been indispensable. The conventional PWOPC is capable of reducing CD variation at off-focus-off-dose conditions for the worst hotspot but some new weak points might be generated due to over compensation from compromising with the worst hotspot. In this paper, a so-called “multiple-step process aware OPC”, was demonstrated for maintaining better process window for all hotspots via damascene metal layer in 43nm half-pitch design. Through isolating the hotspots from the chip layout, different CD tolerances can be applied for the various types of hotspots to avoid the conflicts between different requirements. Increased levels of CD-tolerance could be applied in the multiple-step PWOPC flow for the layout with a great number of weak points. The ultimate aim of the multiple-step PWOPC operation is maintaining sufficient process window for entire layout. The performance comparison was carried out among nominal OPC, conventional PWOPC and multiple-step PWOPC flows for contour CD within appropriate process window, turn around time of layout correction and CD distribution of hotspots.