Spacer-assisted pitch multiplication is a patterning technique that is used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, a combination of lithography, deposition and etch processes, produce a repeating, non-uniform grating of space / line CDs. It has been shown that for spacer-assisted double patterning (SADP), where the lithography pitch is doubled, pitch walk can be reduced by controlling the exposure dose such that the uniformity of the final SADP spaces defined by the core resist mandrel (S1) is balanced with the final SADP space defined by the distance between adjacent SADP lines (S2). For higher pitch multiplications, starting with spacer-assisted quadruple patterning (SAQP) reducing systematic pitch walk with exposure dose becomes more complex.
Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.
Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.
In the discussion of edge placement error (EPE), we proposed interactive pattern fidelity error (IPFE) as an indicator to judge pass/fail of integrated patterns. IPFE consists of lower and upper layer EPEs (CD and center of gravity: COG) and overlay, which is decided from the combination of each maximum variation. We succeeded in obtaining the IPFE density function by Monte Carlo simulation. In the results, we also found that the standard deviation (σ) of each indicator should be controlled by 4.0σ, at the semiconductor grade, such as 100 billion patterns per die. Moreover, CD, COG and overlay were analyzed by analysis of variance (ANOVA); we can discuss all variations from wafer to wafer (WTW), pattern to pattern (PTP), line edge roughness (LWR) and stochastic pattern noise (SPN) on an equal footing. From the analysis results, we can determine that these variations belong to which process and tools. Furthermore, measurement length of LWR is also discussed in ANOVA. We propose that the measurement length for IPFE analysis should not be decided to the micro meter order, such as >2 μm length, but for which device is actually desired.
Extreme UV(EUV) technology must be potential solution for sustainable scaling, and its adoption in high volume manufacturing(HVM) is getting realistic more and more. This technology has a wide capability to mitigate various technical problem in Multi-patterning (LELELE) for via hole patterning with 193-i. It induced local pattern fidelity error such like CDU, CER, Pattern placement error. Exactly, EUV must be desirable scaling-driving tool, however, specific technical issue, named RLS (Resolution-LER-Sensitivity) triangle, obvious remaining issue. In this work, we examined hole patterning sensitizing (Lower dose approach) utilizing hole patterning restoration technique named “CD-Healing” as post-Litho. treatment.
Both local variability and optical proximity correction (OPC) errors are big contributors to the edge placement error (EPE) budget which is closely related to the device yield. The post-litho contact hole healing will be demonstrated to meet after-etch local variability specifications using a low dose, 30mJ/cm2 dose-to-size, positive tone developed (PTD) resist with relevant throughput in high volume manufacturing (HVM). The total local variability of the node 5nm (N5) contact holes will be characterized in terms of local CD uniformity (LCDU), local placement error (LPE), and contact edge roughness (CER) using a statistical methodology. The CD healing process has complex etch proximity effects, so the OPC prediction accuracy is challenging to meet EPE requirements for the N5. Thus, the prediction accuracy of an after-etch model will be investigated and discussed using ASML Tachyon OPC model.
KEYWORDS: Lithography, Logic, Optical lithography, Etching, Metals, Control systems, Computer simulations, Photomasks, Extreme ultraviolet, Semiconducting wafers, TCAD, Back end of line, Front end of line
As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line.
In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.
In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5- nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16- nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.
In our previous paper dealing with multi-patterning, we proposed a new indicator to quantify the quality of final wafer pattern transfer, called interactive pattern fidelity error (IPFE). It detects patterning failures resulting from any source of variation in creating integrated patterns. IPFE is a function of overlay and edge placement error (EPE) of all layers comprising the final pattern (i.e. lower and upper layers). In this paper, we extend the use cases with Via in additional to the bridge case (Block on Spacer). We propose an IPFE budget and CD budget using simple geometric and statistical models with analysis of a variance (ANOVA). In addition, we validate the model with experimental data. From the experimental results, improvements in overlay, local-CDU (LCDU) of contact hole (CH) or pillar patterns (especially, stochastic pattern noise (SPN)) and pitch walking are all critical to meet budget requirements. We also provide a special note about the importance of the line length used in analyzing LWR. We find that IPFE and CD budget requirements are consistent to the table of the ITRS’s technical requirement. Therefore the IPFE concept can be adopted for a variety of integrated structures comprising digital logic circuits. Finally, we suggest how to use IPFE for yield management and optimization requirements for each process.
Multi-patterning has been adopted widely in high volume manufacturing as 193 immersion extension, and it becomes realistic solution of nano-order scaling. In fact, it must be key technology on single directional (1D) layout design  for logic devise and it becomes a major option for further scaling technique in SAQP. The requirement for patterning fidelity control is getting savior more and more, stochastic fluctuation as well as LER (Line edge roughness) has to be micro-scopic observation aria.
In our previous work, such atomic order controllability was viable in complemented technique with etching and deposition . Overlay issue form major potion in yield management, therefore, entire solution is needed keenly including alignment accuracy on scanner and detectability on overlay measurement instruments. As EPE (Edge placement error) was defined as the gap between design pattern and contouring of actual pattern edge, pattern registration in single process level must be considerable. The complementary patterning to fabricate 1D layout actually mitigates any process restrictions, however, multiple process step, symbolized as LELE with 193-i, is burden to yield management and affordability. Recent progress of EUV technology is remarkable, and it is major potential solution for such complicated technical issues. EUV has robust resolution limit and it must be definitely strong scaling driver for process simplification. On the other hand, its stochastic variation such like shot noise due to light source power must be resolved with any additional complemented technique.
In this work, we examined the nano-order CD and profile control on EUV resist pattern and would introduce excellent accomplishments.
Proc. SPIE. 9779, Advances in Patterning Materials and Processes XXXIII
KEYWORDS: Semiconductors, Optical lithography, Etching, Error analysis, Manufacturing, Inspection, Scanning electron microscopy, Process control, Wafer inspection, Plasma etching, Error control coding, Semiconducting wafers, System on a chip, Overlay metrology, Device simulation, Tin
We discuss edge placement errors (EPE) for multi-patterning of Mx critical layers using ArF lithography. Specific focus is placed on the block formation part of the process. While plenty of literature characterization data exist on spacer formation, only limited published data is available on block processes. We analyze the accuracy of placing blocks relative to narrow spacers. Many publications calculate EPE assuming Gaussian distributions for key process variations contributing to EPE. For practical reasons, each contributor is measured on dedicated test structures. In this work, we complement such analysis and directly measure the EPE in product. We perform high density sampling of blocks using CDSEM images and analyze all feature edges of interest. We find that block placement errors can be very different depending on their local design context. Specifically we report on 2 block populations (further called block A and B) which have a 4x different standard deviation. We attribute this to differences in local topography (spacer shape) and interaction with the plasma-etch process design. Block A (on top of the ‘core space’ S1) has excellent EPE uniformity of ~1 nm while block B (on top of ‘gap space’ S2) has degraded EPE control of ~4 nm. Finally, we suggest that the SOC etch process is at the origin on positioning blocks accurately on slim spacers, helping the manufacturability of spacer-based patterning techniques, and helping its extension toward the 5nm node.
In this paper the Arrhenius behavior of blur upon extreme ultraviolet (EUV) exposure is investigated through variation of the post-exposure bake (PEB) temperature. In this way, thermally activated parameters that contribute to blur (such as acid/base diffusion) can be separated from nonthermally activated parameters (such as secondary electron blur). The experimental results are analyzed in detail using multiwavelength resist modeling based on the continuum approach and through fitting of the EUV data using stochastic resist models. The extracted blur kinetics display perfectly linear Arrhenius behavior, indicating that there is no sign for secondary electron blur at 22-nm half pitch. At the lowest PEB setting the total blur length is ∼4 nm, indicating that secondary electron blur should be well below that. The stochastic resist model gives a best fit to the current data set with parameters that result in a maximum probability of acid generation at 2.4 nm from the photon absorption site. Extrapolation of the model predicts that towards the 16-nm half pitch the impact on sizing dose is minimal and an acceptable exposure latitude is achievable. In order to limit the impact on linewidth roughness at these dimensions it will be required to control acid diffusion to ∼5 nm.
EUV lithography is one of the most promising technologies for the fabrication of beyond 30nm HP generation devices.
However, it is well-known that EUV lithography still has significant challenges. A great concern is the change of resist
material for EUV resist process. EUV resist material formulations will likely change from conventional-type materials.
As a result, substrate dependency needs to be understood.
TEL has reported that the simulation combined with experiments is a good way to confirm the substrate dependency. In
this work the application of HMDS treatment and SiON introduction, as an underlayer, are studied to cause a footing of
resist profile. Then, we applied this simulation technique to Samsung EUV process. We will report the benefit of this
simulation work and effect of underlayer application.
Regarding the etching process, underlayer film introduction could have significant issues because the film that should be
etched off increases. For that purpose, thinner films are better for etching. In general, thinner films may have some
coating defects. We will report the coating coverage performance and defectivity of ultra thin film coating.
In this work we present insights into RLS trade-offs by combining experimental data mining and resist modeling and
simulation techniques with a development rate monitor (DRM). A DRM provides experimentally-determined
dissolution characteristics for a given resist process and potentially can be used to produce a more accurate model
description of the process. This work presents experimentally-determined dissolution characteristics for ultra-thin
(50nm) EUV resist films as a function of material type and developer conditions and their impact to RLS trade-offs.
Resist models are created with DRM data for its dissolution characteristics and used in subsequent simulations to gain
fundamental understanding of EUV lithographic performance. In addition to typical lithographic quality metrics
(exposure latitude, DOF), the interaction of resist properties (ie, de-protection kinetics and dissolution) with processing
techniques are also discussed. Finally, a description of the RLS trade-off with respect to resist properties and process
conditions is discussed.
In this paper the Arrhenius behavior of blur upon EUV exposure is investigated through variation of the PEB
temperature. In this way, thermally activated parameters that contribute to blur (such as acid/base diffusion) can be
separated from non-thermally activated parameters (such as secondary electron blur). The experimental results are
analyzed in detail using multi-wavelength resist modeling based on the continuum approach and through fitting of the
EUV data using stochastic resist models. The extracted blur kinetics display perfectly linear Arrhenius behavior,
indicating that there is no sign for secondary electron blur at 22nm half pitch. At the lowest PEB setting the total blur
length is ~4nm, indicating that secondary electron blur should be well below that. The stochastic resist model gives a
best fit to the current data set with parameters that result in a maximum probability of acid generation at 2.4nm from the
photon absorption site. Extrapolation of the model predicts that towards the 16nm half pitch the impact on sizing dose is
minimal and an acceptable exposure latitude is achievable. In order to limit the impact on line width roughness at these
dimensions it will be required to control acid diffusion to ~5nm.
Dual-tone development (DTD) has been previously proposed as a potential cost-effective double patterning technique1.
DTD was reported as early as in the late 1990's2. The basic principle of dual-tone imaging involves processing exposed
resist latent images in both positive tone (aqueous base) and negative tone (organic solvent) developers. Conceptually,
DTD has attractive cost benefits since it enables pitch doubling without the need for multiple etch steps of patterned
resist layers. While the concept for DTD technique is simple to understand, there are many challenges that must be
overcome and understood in order to make it a manufacturing solution.
Previous work by the authors demonstrated feasibility of DTD imaging for 50nm half-pitch features at 0.80NA (k1 =
0.21) and discussed challenges lying ahead for printing sub-40nm half-pitch features with DTD. While previous
experimental results suggested that clever processing on the wafer track can be used to enable DTD beyond 50nm halfpitch,
it also suggest that identifying suitable resist materials or chemistries is essential for achieving successful imaging
results with novel resist processing methods on the wafer track. In this work, we present recent advances in the search
for resist materials that work in conjunction with novel resist processing methods on the wafer track to enable DTD.
Recent experimental results with new resist chemistries, specifically designed for DTD, are presented in this work. We
also present simulation studies that help and support identifying resist properties that could enable DTD imaging, which
ultimately lead to producing viable DTD resist materials.
The challenge in obtaining good resist performance in terms of resolution, line width roughness and sensitivity at EUV
wavelength forces to make more efficient use of photons that reach the wafer plane than has been the case for traditional
optical lithography. Theory demonstrates that the current absorbance levels of EUV resists are quite far from optimal and
absorbance should be increased. The most attractive pathway to achieve this is by increasing the fluorine content of EUV
resists. The viability of this approach has been demonstrated using non-chemically amplified PMMA as model resist and
comparing its photospeed with a fluorinated analogue. It has been demonstrated that the photospeed increases due to
improved resist absorbance by ~1.5X, which is close to 1.7X that is predicted by the difference in absorbance.
Further modeling studies support the experimental results and indicate an optimum for total film absorbance of ~0.20-
0.25. Compared to current platforms this would correspond to an increase in photospeed by ~1.7X which is accompanied with an improvement in LWR of ~1.14X. Combining this approach with the trends in EUV resists to increase PAG loading and include sensitizer in order to improve photospeed will likely provide a path for EUV resists that will meet the specifications that are required for the 32nm and 22nm node.
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across
wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across
wafer systematic variations, compensation by exposure dose and/or post exposure bake (PEB) temperature have been
proposed. These compensation strategies often focus on a specific structure without evaluating how process
compensation impacts the CDU of all structures to be printed in a given design.
In one previous study limited to a single resist and minimal coater/developer and scanner variations, the authors
evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias
and CDU. For the process studied, it was found that using PEB temperature to control CD across wafer was preferable to
using dose compensation. In another previous study, the impact of resist design was explored to understand how resist
design, as well as coater/developer and scanner processing, impact process induced bias (PIB). The previous PIB studies
were limited to a single illumination case and explore the effect of PIB on only L/S structures.
It is the goal of this work to understand additionally how illumination design and mask design, as well as resist design
and coater/developer and scanner processing, impact process induced bias (PIB)/OPC integrity.
The ever-shrinking circuit device dimensions challenge lithographers to explore viable patterning for the 32 nm halfpitch
node and beyond. Significant improvements in immersion lithography have allowed extension of optical
lithography down to 45 nm node and likely into early 32 nm node development. In the absence of single-exposure
patterning solutions, double patterning techniques are likely to extend immersion lithography for 32 nm node
manufacturing. While several double patterning techniques have been proposed as viable manufacturing solutions, cost,
along with technical capability, will dictate which candidate is adopted by the industry.
Dual-tone development (DTD) has been proposed as a potential cost-effective double patterning technique.1 Dual-tone
development was reported as early as in the late 1990's by Asano.2 The basic principle of dual-tone imaging involves
processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent)
developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple
etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many
challenges that must be overcome and understood in order to make it a manufacturing solution.
This work presents recent advances and challenges associated with DTD. Experimental results in conjunction with
simulations are used to understand and advance learning for DTD. Experimental results suggest that clever processing
on the wafer track can be used to enable DTD beyond 45 nm half-pitch dimensions for a given resist process. Recent
experimental results also show that DTD is capable of printing <0.25 k1-factor features with an ArF immersion scanner.
Simulation results showing co-optimization of process variables, illumination conditions, and mask properties are
The objective of this work is to understand, from a simulation perspective, how current EUV resist chemistries compare to mature 193nm (ArF) photoresist systems. Accurate resist models for EUV resists may be developed using the same in-house calibration methodology used for ArF resists. Using this methodology, key resist properties, such as optical density, dissolution behavior, and imaging characteristics, are correlated to model parameters that have a significant impact on resist imaging performance. Such resist models, once calibrated, are used to make predictions of key lithographic metrics, such as MEF and process latitude. In this work, model calibration results for ArF and EUV resist systems are compared and the resulting resist models are used to contrast fundamental resist behavior at the ArF and EUV wavelengths.
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer variations, compensation by exposure dose and/or PEB temperature, have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In a previous study, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, both metrics demonstrated that using PEB temperature to control across wafer CD variation was preferable to using dose compensation.
The previous study was limited to a single resist and variations to track and scanner processing were kept to a minimum. Further examination of additional resist materials has indicated that significant variation in dose and PEB temperature induced CD biases exist from material to material. It is the goal of this work to understand how resist design, as well as track and scanner processing, impact process induced bias (PIB). This is accomplished by analyzing full resist models for a range of resists that exhibit different dose and PEB temperature PIB behavior. From these models, the primary resist design contributors to PIB are isolated. A sensitivity analysis of the primary resist design as well as track and scanner processing effects will also be simulated and presented.
Double exposure lithography processes can offer a significant yield enhancement for challenging circuit designs. Many
decomposition techniques (i.e. the process of dividing the layout design into first and second exposures) are possible, but
the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first
exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g.
dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist
features" or PrAFs) are designed to support the process window of critical features much like the role of the sub-resolution
assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more
design options, and hence a greater process exploration space, than are available for SRAFs.
A decomposition scheme using PrAFs was developed for a gate level process. A critical driver of the work was to
deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single-exposure process. A
variety of PrAF techniques were investigated, including block type features, variable-pitch PrAFs, and constant assist-to-feature
spacing (similar to SRAF placement). A PrAF scheme similar to standard SRAF rules was chosen as the optimal
solution. The resulting ACLV benefits occurred mainly in the intermediate pitch range. For dense pitches, the ACLV
was mostly unchanged, since in that regime neither process used assist features. The PrAF process showed a benefit of
10-44% improvement of ACLV in the mid-range pitches, but up to 18% worse ACLV for isolated pitches. Thus, the
optimal double exposure solution was a combination of SRAFs and PrAFs that achieved the ACLV benefits of both.
This paper addresses a challenge to the concept of process window OPC (PWOPC) by investigating the dimensional control of effectively non-printing features to improve the process window (PW) of the primary layout. It is shown based on a double exposure (DE) alternating phase-shift mask (altPSM) process that neglecting the impact of final mask dimensions forming intermediate images in resist (which are subsequently removed with a second exposure) potentially leads to a significant variation in the available focus budget of neighboring linewidth-critical feature dimensions. Various rules-based and model-based options of introducing virtual OPC targets into the OPC flow are discussed as an efficient mean to allow the OPC to take process window considerations into account. The paper focuses especially on the mechanics of how in detail those virtual targets support the beneficial OPC convergence of affected edges. Finally, experimental proof is shown that introducing non-printing, virtual targets being considered as actual targets during OPC ensures enhanced through focus line width stability and hence making the OPC solution well aware of process window aspects.
DFM (Design for Manufacturing) has become a buzzword for lithography since the 90nm node. Implementing DFM intelligently can boost yield rates and reliability in semiconductor manufacturing significantly. However, any restriction on the design space will always result in an area loss, thus diminishing the effective shrink factor for a given technology. For a lithographer, the key task is to develop a manufacturable process, while not sacrificing too much area. We have developed a high performing lithography process for attenuated gate level lithography that is based on aggressive illumination and a newly optimized SRAF placement schemes. In this paper we present our methodology and results for this optimization, using an anchored simulation model. The wafer results largely confirm the predictions of the simulations. The use of aggressive SRAF (Sub Resolution Assist Features) strategy leads to reduction of forbidden pitch regions without any SRAF printing. The data show that our OPC is capable of correcting the PC tip to tip distance without bridging between the tips in dense SRAM cells. SRAF strategy for various 2D cases has also been verified on wafer. We have shown that aggressive illumination schemes yielding a high performing lithography process can be employed without sacrificing area. By carefully choosing processing conditions, we were able develop a process that has very little restrictions for design. In our approach, the remaining issues can be addressed by DFM, partly in data prep procedures, which are largely area neutral and transparent to the designers. Hence, we have shown successfully, that DFM and effective technology shrinks are not mutually exclusive.
We present a systematic analysis of the imaging performance for a 0.93 numerical aperture (NA) state-of-the-art immersion lithography scanner and we compare this performance to its dry NA=0.93 counterpart. The increased depth of focus (DOF) enabled by immersion lithography presents a set of advantages for semiconductor manufacturing which we explore in this article. First, we show that 0.93 NA immersion prevents, for a 65nm gate-level process, the need for imposing pitch restrictions with an attenuated-PSM solution; something not possible with an equivalent "dry" process. Second, we demonstrate the superior critical dimension uniformity (CDU) of an immersion process in the presence of realistic focus variations typically encountered in semiconductor manufacturing. Third, we confirm that the through-pitch behavior of "wet" and "dry" scanners is well matched, enabling the possibility of transferring optical proximity corrections (OPC) between the two types of lithography scanners. The transferability of OPC is key to enabling a fast insertion of immersion lithography into the manufacturing process for the 65nm and 45nm nodes. Finally, we conclude that, from an imaging perspective, immersion is ready for high-volume manufacturing.
This paper will consider the basic concepts of resist blur in a chemically amplified resist process, and the implications of this blur to lithography. In particular, use of a double Gaussian form for the resist blur will be explored. A simple lithographic model utilizing a double Gaussian resist blur was developed and applied to the rapid calculation of lithographic CDs. A typical gate patterning problem was modeled, both with and without assist features, using several different resist blur functions. The OPC treatment was found to be profoundly affected by the resist blur, especially the long-range component. The MEF of small pitch patterns was a sensitive indicator of the short-range blur. The rapid modeling capability allowed large Monte Carlo simulations to explore CD variation at different pitches, pointing out pitches that were particularly vulnerable to CD variation.
The implementation of alternating phase shifted mask lithography for the poly-conductor level of IBM's leading edge 65nm microprocessor is described. Very broad and 'resolution-enhancement-technology generic' design rules, referred to as radical design restrictions, are demonstrated to be key enablers of alternating phase shifted mask design. The benefit of these radical design restrictions over conventional design rules and other alternating phase shifted mask design approaches is detailed for key aspects of the design flow.
This paper attempts to shed more light on the widely acknowledged need to improve the manufacturabilty of itnegrated chip layouts for sub-100nm technology nodes. After reviewing the parametric performance targets and tiem constaints of the 65nm and 45nm technology nodes, the paper elaborates on the principles of popular resolution enhancement techniques, their impact on chip layouts, and the opportunity for borad layout improvement which they afford. Finally, the viability and feasibility of layout optimization based on a design-for-manufacturability mantra and enabled through "radically design restrictions" is explored.
This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.
An enhanced methodology of generating exposure tool specification, specifically lens specification, using alternating phase shift mask (AltPSM) features as anchor structures is introduced in this paper. The use of AltPSM as a resolution enhancement technique requires a unique set of exposure tool requirement on lens and body functionality. The lens aberration level requirement and sensitivity of certain type of Zernike term need to be identified for optimization of the lens for AltPSM application. The NA/Sigma scaling of AltPSM with current level of aberration is discussed briefly. We also extend the response surface CD model to a quadratic model that includes cross talk among Zernike terms. New definition of CD aberration sensitivity based on the quadratic model allows the sensitivity term to include the crosstalk effect. Specifications for aberration levels were established by Monte Carlo CD simulation, taking into account the inherent correlation between Zernike coefficients that we determine from analysis of the pupil Power Spectral Density. Difference on the phasemap behavior and final calculated specification are compared for the correlated and uncorrelated Zernike case. Finally we briefly discuss the flare effect on trim mask exposure and the issues in AltPSM EMF simulation in a high NA regime. Similar treatment for image placement indicated it is as critical as CD for 70nm mode AltPSM application.
The likely possibility of having to support the 70 nm technology node with 193 nm lithography is lithography. The extremely significant resolution challenges and the ability of strong resolution enhancement techniques (RET) to meet them, is discussed. Evidence is presented that all strong RET impact the design flow by imposing nontrivial design restrictions. Data from an in-depth alternating phase shifted mask design feasibility assessment, conducted on the poly-gate level of the 180 nm technology node, is presented to give an outlook on the feasibility of RET-enabled design flows. Anticipated complications in taking such RET-enabled design flows to the complexity required for multiple critical levels of the 70nm node are discussed. An EDA solution focusing on complete integration of RET layout manipulations into the design flow is contrasted to an approach focusing on complex, optimized design rule comprises.
New degrees of freedom can be optimized in mask shapes
when the source is also adjustable, because required image symmetries can be provided by the source rather than the collected wave front. The optimized mask will often consist of novel sets of shapes that are quite different in layout from the target integrated circuit patterns. This implies that the optimization algorithm should have good global convergence
properties, since the target patterns may not be a suitable starting solution. We have developed an algorithm that can optimize mask and source without using a starting design. Examples are shown where the
process window obtained is between two and six times larger than that achieved with standard reticle enhancement techniques (RET). The optimized
masks require phase shift, but no trim mask is used. Thus far we can only optimize two-dimensional patterns over small fields (periodicities
of ;1 mm or less), though patterns in two separate fields can be jointly optimized for maximum common window under a single source. We also discuss mask optimization with fixed source, source optimization
with fixed mask, and the retargeting of designs in different mask regions to provide a common exposure level.
The continuing drive to reduce feature size is forcing resist processes to be tailored to specific levels, e.g. contact holes or isolated lines. Resist contrast, absorption, diffusion length and development characteristics are among the customized variables. For the most part, resist tone has not been among these variables, and the bulk of advanced lithography is done with positive tone resist processes. This paper will explore the optimum process tone for various feature types, and will include simple theoretical guidelines to help with this decision. Narrow resist lines are found to print best with a positive tone process while narrow trench geometries are found to print best with a negative tone process. Simple development bias models appear to accurately capture this behavior and are in agreement with full simulation.
The maturity and acceptance of top surface imaging (TSI) technology has been hampered by several factors including inadequate resist sensitivity and silylation contrast, defects and line edge roughness and equipment performance/reliability issues. We found that the use of a chemically amplified resist can improve the sensitivity by a factor of 1.5 - 2X, without compromising line edge roughness. While the post-silylation contrast of this chemically amplified material is poor ((gamma) < 1), the post-etch contrast is excellent ((gamma) >> 10) and the use of advanced silylation chemistries (disilanes) can further reduce the dose-to-size and increase the contrast. We have also demonstrated that using sulfur dioxide in the plasma etch process can improve the sidewall passivation of the resist lines, thus reducing the overall line edge roughness. Finally, we have been able to successfully use the TSI process to pattern deep sub-micron polysilicon and metal patterns.
The use of attenuated phase-shift masking materials is being considered as one of the key resolution enhancement techniques for sub-0.18 micrometers lithography. In addition to proper optical performance, films for use at DUV and 193 nm wavelengths require suitable plasma etch characteristics and stability at mask exposure levels of pulse excimer lasers. This may limit practical materials to those which allow suitably volatile etch bi-products and possess stable stoichiometric composition. Several film families have been produced which can deliver a (pi) phase shift and 4 - 15% transmission within a single films thickness including Al/AlN, MoSiO, TaSiO, Zr/ZrN, SixNy, and TaN/Si3N4. Of these materials, TaSiO, SixNy, and TaN/Si3N4, allow for adequate plasma etch performance with selectivity to fused silica and resist. Excimer laser 193 nm exposure at fluences corresponding to mask exposure levels show some degree of optical degradation of materials prone to oxidation.